X86 fixes, 2015-11-17
Two X86 fixes, hopefully in time for -rc1. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJWS3rNAAoJECgHk2+YTcWm34gP/2H2kzNYQMKOib7dXIarV+Sg 8fAN+wyL2px5GUjTuwzfT81q2aaoTnHIwcKjrVUt6hy5KLPuwKc2ZlaR66Smu6LZ 6RgPtaDE8NvUmaxOz+Vv9xic8X7YxpoqDJUIGc8apG0/nf+3ta0UY/kMg9zH9Zrb iYHtZlKfVyHwXZNGKs1k8RWLWaWKmAwHpreXpIJ6sxmKb8Q7ngRz+UdRTGkPEsoo Jyyt0X29J67Q9HtJKyaufjBl6XLo7tpfR2L8ups8Gi8+PEizBCNe4G1J+B8jEHqf wXM5elEjnLG5nwWh8mc5CTvi7OLmQz3TjY33aMlw1iuxol6VH2ApGgy6/XCBmFOO NhBsFwZqN/rCKsd+vRUt1BQzD/czFt/f2ln6AGm77skr9/QV07KIAZ8A7kos3l2q OKVYD0CpYtyKupEYWZrMqXYP9uHzG5TqqWsMqeFvmbIB2rijORnngCnkcMl6QNJi kViYDM5X15aeIQbB+al+rqwsB0NIkeLOrqJO1GYu4udhkYLLqVrCORWpWLWYaq1c iNBdEdlPjOSaipO8HKperZKSHrQKnOQmvOCvRtbpusNoHqnQZ8w6AhzsAv0S25kA 0WKJBkNh386sfj5lcL8WSBiJgKhNBrCmbehr2HI0zMynnpHBFzM28GpRMUfAlzhk 8gRURPaw0zDs6xLL7/dA =IkkR -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging X86 fixes, 2015-11-17 Two X86 fixes, hopefully in time for -rc1. # gpg: Signature made Tue 17 Nov 2015 19:06:53 GMT using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" * remotes/ehabkost/tags/x86-pull-request: target-i386: Disable rdtscp on Opteron_G* CPU models target-i386: Fix mulx for identical target regs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
55db5eeeb7
@ -347,8 +347,25 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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.driver = "qemu32" "-" TYPE_X86_CPU,\
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.property = "popcnt",\
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.value = "on",\
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},{\
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.driver = "Opteron_G2" "-" TYPE_X86_CPU,\
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.property = "rdtscp",\
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.value = "on",\
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},{\
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.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
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.property = "rdtscp",\
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.value = "on",\
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},{\
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.driver = "Opteron_G4" "-" TYPE_X86_CPU,\
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.property = "rdtscp",\
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.value = "on",\
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},{\
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.driver = "Opteron_G5" "-" TYPE_X86_CPU,\
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.property = "rdtscp",\
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.value = "on",\
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},
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#define PC_COMPAT_2_3 \
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PC_COMPAT_2_4 \
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HW_COMPAT_2_3 \
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@ -1244,8 +1244,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_DE | CPUID_FP87,
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.features[FEAT_1_ECX] =
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CPUID_EXT_CX16 | CPUID_EXT_SSE3,
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/* Missing: CPUID_EXT2_RDTSCP */
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.features[FEAT_8000_0001_EDX] =
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
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CPUID_EXT2_LM | CPUID_EXT2_FXSR |
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CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
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CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
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CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
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@ -1273,8 +1274,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.features[FEAT_1_ECX] =
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CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
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CPUID_EXT_SSE3,
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/* Missing: CPUID_EXT2_RDTSCP */
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.features[FEAT_8000_0001_EDX] =
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
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CPUID_EXT2_LM | CPUID_EXT2_FXSR |
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CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
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CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
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CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
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@ -1305,8 +1307,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
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CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
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CPUID_EXT_SSE3,
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/* Missing: CPUID_EXT2_RDTSCP */
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.features[FEAT_8000_0001_EDX] =
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
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CPUID_EXT2_LM |
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CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
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CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
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CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
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@ -1340,8 +1343,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
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CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
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CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
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/* Missing: CPUID_EXT2_RDTSCP */
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.features[FEAT_8000_0001_EDX] =
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
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CPUID_EXT2_LM |
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CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
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CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
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CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
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@ -3848,8 +3848,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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break;
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#ifdef TARGET_X86_64
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case MO_64:
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tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
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tcg_gen_mulu2_i64(cpu_T[0], cpu_T[1],
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cpu_T[0], cpu_regs[R_EDX]);
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tcg_gen_mov_i64(cpu_regs[s->vex_v], cpu_T[0]);
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tcg_gen_mov_i64(cpu_regs[reg], cpu_T[1]);
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break;
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#endif
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}
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