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The other half of the mul64 rework. Sorry for the breakage, I committed

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an incomplete version of what I tested.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3454 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-10-26 22:35:02 +00:00
parent 7878ff6bc7
commit 5592a750b9
3 changed files with 7 additions and 5 deletions
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2
host-utils.c
View File

@ -25,6 +25,8 @@
#include "vl.h"
//#define DEBUG_MULDIV
/* Long integer helpers */
static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
{

6
target-i386/helper.c
View File

@ -3724,7 +3724,7 @@ void helper_mulq_EAX_T0(void)
{
uint64_t r0, r1;
mulu64(&r1, &r0, EAX, T0);
mulu64(&r0, &r1, EAX, T0);
EAX = r0;
EDX = r1;
CC_DST = r0;
@ -3735,7 +3735,7 @@ void helper_imulq_EAX_T0(void)
{
uint64_t r0, r1;
muls64(&r1, &r0, EAX, T0);
muls64(&r0, &r1, EAX, T0);
EAX = r0;
EDX = r1;
CC_DST = r0;
@ -3746,7 +3746,7 @@ void helper_imulq_T0_T1(void)
{
uint64_t r0, r1;
muls64(&r1, &r0, T0, T1);
muls64(&r0, &r1, T0, T1);
T0 = r0;
CC_DST = r0;
CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));

4
target-mips/op.c
View File

@ -876,13 +876,13 @@ void op_msubu (void)
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
void op_dmult (void)
{
CALL_FROM_TB4(muls64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1);
CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
RETURN();
}
void op_dmultu (void)
{
CALL_FROM_TB4(mulu64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1);
CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
RETURN();
}
#endif