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My core2duo patch introduced a vague statement of "missing features" in

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the CPUID specification. This patch addresses this by specifying exactly 
what is missing.
While going along the missing CPUID entries I also stumbled across 
invalid and missing CPUID #defines while comparing them to the Intel 
Documentation. This patch also addresses these. I found them too minor 
to split them up in a separate patch.

Furthermore I looked through CPUID functions > 5 and realized that it 
should be safe to bump the level to 10. I tried booting Linux with that 
and it worked fine.


Signed-off-by: Alexander Graf <agraf@suse.de>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5350 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2008-09-29 13:55:36 +00:00
parent e6a6d5abc6
commit 558fa8361b
3 changed files with 41 additions and 9 deletions
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12
target-i386/cpu.h
View File

@ -298,6 +298,7 @@
#define CPUID_PBE (1 << 31)
#define CPUID_EXT_SSE3 (1 << 0)
#define CPUID_EXT_DTES64 (1 << 2)
#define CPUID_EXT_MONITOR (1 << 3)
#define CPUID_EXT_DSCPL (1 << 4)
#define CPUID_EXT_VMX (1 << 5)
@ -308,8 +309,15 @@
#define CPUID_EXT_CID (1 << 10)
#define CPUID_EXT_CX16 (1 << 13)
#define CPUID_EXT_XTPR (1 << 14)
#define CPUID_EXT_DCA (1 << 17)
#define CPUID_EXT_POPCNT (1 << 22)
#define CPUID_EXT_PDCM (1 << 15)
#define CPUID_EXT_DCA (1 << 18)
#define CPUID_EXT_SSE41 (1 << 19)
#define CPUID_EXT_SSE42 (1 << 20)
#define CPUID_EXT_X2APIC (1 << 21)
#define CPUID_EXT_MOVBE (1 << 22)
#define CPUID_EXT_POPCNT (1 << 23)
#define CPUID_EXT_XSAVE (1 << 26)
#define CPUID_EXT_OSXSAVE (1 << 27)
#define CPUID_EXT2_SYSCALL (1 << 11)
#define CPUID_EXT2_MP (1 << 19)

17
target-i386/helper.c
View File

@ -167,19 +167,22 @@ static x86_def_t x86_defs[] = {
},
{
.name = "core2duo",
/* original is on level 10 */
.level = 5,
.level = 10,
.family = 6,
.model = 15,
.stepping = 11,
/* the original CPU does have many more features that are
* not implemented yet */
/* The original CPU also implements these features:
CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
CPUID_TM, CPUID_PBE */
.features = PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36,
/* The original CPU also implements these ext features:
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3,
.ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
/* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
.xlevel = 0x8000000A,
.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
},
@ -240,7 +243,7 @@ static x86_def_t x86_defs[] = {
.family = 6,
.model = 2,
.stepping = 3,
.features = PPRO_FEATURES | PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
.xlevel = 0x80000008,
/* XXX: put another string ? */

21
target-i386/op_helper.c
View File

@ -1956,6 +1956,27 @@ void helper_cpuid(void)
ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
EDX = 0;
break;
case 6:
/* Thermal and Power Leaf */
EAX = 0;
EBX = 0;
ECX = 0;
EDX = 0;
break;
case 9:
/* Direct Cache Access Information Leaf */
EAX = 0; /* Bits 0-31 in DCA_CAP MSR */
EBX = 0;
ECX = 0;
EDX = 0;
break;
case 0xA:
/* Architectural Performance Monitoring Leaf */
EAX = 0;
EBX = 0;
ECX = 0;
EDX = 0;
break;
case 0x80000000:
EAX = env->cpuid_xlevel;
EBX = env->cpuid_vendor1;