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s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL

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Take care of properly taking the modulo of the count. We might later
want to come back and create a variant of VERLL where the base register
is 0, resulting in an immediate.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
This commit is contained in:
David Hildenbrand 2019-04-11 11:19:38 +02:00
parent c3838aaae0
commit 55236da222
4 changed files with 98 additions and 0 deletions
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4
target/s390x/helper.h
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@ -198,6 +198,10 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)

3
target/s390x/insn-data.def
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@ -1146,6 +1146,9 @@
F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
/* VECTOR POPULATION COUNT */
F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */

60
target/s390x/translate_vx.inc.c
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@ -185,6 +185,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_2(v1, v2, gen) \
tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16, gen)
#define gen_gvec_2s(v1, v2, c, gen) \
tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16, c, gen)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@ -1845,3 +1848,60 @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_andi_i32(t0, b, 31);
tcg_gen_rotl_i32(d, a, t0);
tcg_temp_free_i32(t0);
}
static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_andi_i64(t0, b, 63);
tcg_gen_rotl_i64(d, a, t0);
tcg_temp_free_i64(t0);
}
static DisasJumpType op_verllv(DisasContext *s, DisasOps *o)
{
const uint8_t es = get_field(s->fields, m4);
static const GVecGen3 g[4] = {
{ .fno = gen_helper_gvec_verllv8, },
{ .fno = gen_helper_gvec_verllv16, },
{ .fni4 = gen_rll_i32, },
{ .fni8 = gen_rll_i64, },
};
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
{
const uint8_t es = get_field(s->fields, m4);
static const GVecGen2s g[4] = {
{ .fno = gen_helper_gvec_verll8, },
{ .fno = gen_helper_gvec_verll16, },
{ .fni4 = gen_rll_i32, },
{ .fni8 = gen_rll_i64, },
};
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
gen_gvec_2s(get_field(s->fields, v1), get_field(s->fields, v3), o->addr1,
&g[es]);
return DISAS_NEXT;
}

31
target/s390x/vec_int_helper.c
View File

@ -478,3 +478,34 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VPOPCT(8)
DEF_VPOPCT(16)
#define DEF_VERLLV(BITS) \
void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, \
uint32_t desc) \
{ \
int i; \
\
for (i = 0; i < (128 / BITS); i++) { \
const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
\
s390_vec_write_element##BITS(v1, i, rol##BITS(a, b)); \
} \
}
DEF_VERLLV(8)
DEF_VERLLV(16)
#define DEF_VERLL(BITS) \
void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \
uint32_t desc) \
{ \
int i; \
\
for (i = 0; i < (128 / BITS); i++) { \
const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
\
s390_vec_write_element##BITS(v1, i, rol##BITS(a, count)); \
} \
}
DEF_VERLL(8)
DEF_VERLL(16)