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target-ppc: add functions to load/store SPR

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5881 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-12-05 07:21:31 +00:00
parent b2b183c270
commit 54cdcae646
1 changed files with 13 additions and 2 deletions
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15
target-ppc/translate.c
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@ -688,6 +688,17 @@ OPCODES_SECTION opcode_t opc_##name = { \
.oname = stringify(name), \ .oname = stringify(name), \
} }
/* SPR load/store helpers */
static always_inline void gen_load_spr(TCGv t, int reg)
{
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}
static always_inline void gen_store_spr(int reg, TCGv t)
{
tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}
/* Start opcode list */ /* Start opcode list */
GEN_OPCODE_MARK(start); GEN_OPCODE_MARK(start);
@ -1550,10 +1561,10 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
} }
if (prio) { if (prio) {
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR])); gen_load_spr(t0, SPR_PPR);
tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR])); gen_store_spr(SPR_PPR, t0);
tcg_temp_free(t0); tcg_temp_free(t0);
} }
#endif #endif