ppc64: introduce e6500
This introduces e6500 core. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
KONRAD Frederic
David Gibson
parent
d21ee6331e
commit
54a50dae93
@ -693,6 +693,8 @@
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#ifdef TARGET_PPC64
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POWERPC_DEF_SVR("e5500", "e5500",
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CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
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POWERPC_DEF_SVR("e6500", "e6500",
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CPU_POWERPC_e6500, POWERPC_SVR_E500, e6500)
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#endif
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/* PowerPC e500 microcontrollers */
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POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0",
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@ -346,6 +346,7 @@ enum {
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CPU_POWERPC_e500v2_v30 = 0x80210030,
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CPU_POWERPC_e500mc = 0x80230020,
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CPU_POWERPC_e5500 = 0x80240020,
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CPU_POWERPC_e6500 = 0x80400020,
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/* MPC85xx microcontrollers */
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#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
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#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
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@ -4888,6 +4888,7 @@ enum fsl_e500_version {
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fsl_e500v2,
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fsl_e500mc,
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fsl_e5500,
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fsl_e6500,
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};
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static void init_proc_e500(CPUPPCState *env, int version)
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@ -4922,6 +4923,9 @@ static void init_proc_e500(CPUPPCState *env, int version)
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case fsl_e5500:
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ivor_mask = 0x000003FE0000FFFFULL;
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break;
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case fsl_e6500:
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ivor_mask = 0x000003FF0000FFFFULL;
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break;
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}
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gen_spr_BookE(env, ivor_mask);
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gen_spr_usprg3(env);
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@ -4954,6 +4958,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
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tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
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tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
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break;
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case fsl_e6500:
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mmucfg = 0x6510B45;
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env->nb_pids = 1;
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tlbncfg[0] = 0x08052400;
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tlbncfg[1] = 0x40028040;
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break;
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default:
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cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
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}
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@ -4972,6 +4982,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
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l1cfg0 |= 0x1000000; /* 64 byte cache block size */
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l1cfg1 |= 0x1000000; /* 64 byte cache block size */
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break;
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case fsl_e6500:
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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l1cfg0 |= 0x0F83820;
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l1cfg1 |= 0x0B83820;
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break;
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default:
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cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
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}
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@ -5050,7 +5066,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
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&spr_read_generic, SPR_NOACCESS,
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0x00000000);
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/* XXX better abstract into Emb.xxx features */
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if (version == fsl_e5500) {
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if ((version == fsl_e5500) || (version == fsl_e6500)) {
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spr_register(env, SPR_BOOKE_EPCR, "EPCR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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@ -5062,6 +5078,30 @@ static void init_proc_e500(CPUPPCState *env, int version)
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ivpr_mask = (target_ulong)~0xFFFFULL;
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}
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if (version == fsl_e6500) {
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spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Thread identification */
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spr_register(env, SPR_TIR, "TIR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, SPR_NOACCESS,
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0x00000000);
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spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, SPR_NOACCESS,
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0x00000004);
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spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, SPR_NOACCESS,
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0x7FFFFFFC);
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}
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 0;
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env->tlb_type = TLB_MAS;
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@ -5254,6 +5294,55 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
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pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
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POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
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}
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static void init_proc_e6500(CPUPPCState *env)
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{
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init_proc_e500(env, fsl_e6500);
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}
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POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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dc->desc = "e6500 core";
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pcc->init_proc = init_proc_e6500;
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pcc->check_pow = check_pow_none;
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pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
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PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
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PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
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PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
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PPC_FLOAT | PPC_FLOAT_FRES |
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PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
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PPC_FLOAT_STFIWX | PPC_WAIT |
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PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
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PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
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pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
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PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
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pcc->msr_mask = (1ull << MSR_CM) |
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(1ull << MSR_GS) |
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(1ull << MSR_UCLE) |
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(1ull << MSR_CE) |
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(1ull << MSR_EE) |
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(1ull << MSR_PR) |
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(1ull << MSR_FP) |
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(1ull << MSR_ME) |
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(1ull << MSR_FE0) |
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(1ull << MSR_DE) |
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(1ull << MSR_FE1) |
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(1ull << MSR_IS) |
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(1ull << MSR_DS) |
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(1ull << MSR_PX) |
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(1ull << MSR_RI) |
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(1ull << MSR_VR);
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pcc->mmu_model = POWERPC_MMU_BOOKE206;
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pcc->excp_model = POWERPC_EXCP_BOOKE;
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pcc->bus_model = PPC_FLAGS_INPUT_BookE;
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pcc->bfd_mach = bfd_mach_ppc_e500;
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pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
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POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
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}
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#endif
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/* Non-embedded PowerPC */
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