target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
If we want to make better decisions when auto-enabling extensions during realize() we need a way to tell if an user set an extension manually. The RISC-V KVM driver has its own solution via a KVMCPUConfig struct that has an 'user_set' flag that is set during the Property set() callback. The set() callback also does init() time validations based on the current KVM driver capabilities. For TCG we would want a 'user_set' mechanic too, but we would look ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set or not. If we copy what was made in the KVM side we would look for 'user_set' for one into 60+ extension structs spreaded in 3 arrays (riscv_cpu_extensions, riscv_cpu_experimental_exts, riscv_cpu_vendor_exts). We'll still need an extension struct but we won't be using the 'user_set' flag: - 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to what we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'. DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct; - the 'multi_ext_user_opts' hash will be used to store the offset of each extension that the user set via the set() callback, cpu_set_multi_ext_cfg(). For now we're just initializing and populating it - next patch will use it to determine if a certain extension was user set; - cpu_add_multi_ext_prop() is a new helper that will replace the qdev_property_add_static() calls that our macros are doing to populate user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY() for clarity. Note that the non-extension properties in riscv_cpu_options[] still need to be declared via qdev(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230912132423.268494-18-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
Alistair Francis
parent
c72b379127
commit
549cbf789e
@ -162,6 +162,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
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};
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/* Hash that stores user set extensions */
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static GHashTable *multi_ext_user_opts;
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static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
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{
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bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
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@ -1714,6 +1717,8 @@ static void riscv_cpu_init(Object *obj)
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qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
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IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
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#endif /* CONFIG_USER_ONLY */
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multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
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}
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typedef struct RISCVCPUMisaExtConfig {
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@ -1865,108 +1870,118 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
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}
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}
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static Property riscv_cpu_extensions[] = {
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typedef struct RISCVCPUMultiExtConfig {
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const char *name;
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uint32_t offset;
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bool enabled;
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} RISCVCPUMultiExtConfig;
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#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
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{.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
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.enabled = _defval}
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static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
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/* Defaults for standard extensions */
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DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
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DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
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DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
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DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true),
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DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
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DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
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DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true),
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DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
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DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
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DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
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DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
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DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
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DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
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MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
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MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
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MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
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MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
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MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
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MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
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MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
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MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
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MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
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MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
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MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
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MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
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MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
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DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
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DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
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DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
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DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
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DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
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MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
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MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
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MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
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MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
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MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
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DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
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DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
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DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
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DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
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DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
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DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
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DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
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DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
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DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
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DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
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DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
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DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
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DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
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DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
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DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
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DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
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DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
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MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
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MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
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MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
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MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
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MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
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MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
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MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
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MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
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MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
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MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
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MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
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MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
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MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
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MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
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MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
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MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
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MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
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DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
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DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
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DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
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DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
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MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
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MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
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MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
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MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
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DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
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DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
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MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
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MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
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DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
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MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
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DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
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DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
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DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
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DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
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DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
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DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
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DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
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DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
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MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
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MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
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MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
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MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
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MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
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MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
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MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
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MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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static Property riscv_cpu_vendor_exts[] = {
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DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
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DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
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DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
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DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
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DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
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DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
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DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
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DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
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DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
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DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
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DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
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DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
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static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
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MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
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MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
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MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
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MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
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MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
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MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
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MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
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MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
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MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
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MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
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MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
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MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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/* These are experimental so mark with 'x-' */
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static Property riscv_cpu_experimental_exts[] = {
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static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
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/* ePMP 0.9.3 */
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DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
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DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
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DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
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MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
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MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
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MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
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DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
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DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
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MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
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MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
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DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
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DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
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DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
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MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
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MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
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MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
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/* Vector cryptography extensions */
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DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
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DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
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DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
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DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
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DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
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DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
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DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
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DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
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MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
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MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
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MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
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MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
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MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
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MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
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MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
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MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -1989,12 +2004,56 @@ static Property riscv_cpu_options[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
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static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
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bool value;
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if (!visit_type_bool(v, name, &value, errp)) {
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return;
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}
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isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
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g_hash_table_insert(multi_ext_user_opts,
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GUINT_TO_POINTER(multi_ext_cfg->offset),
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(gpointer)value);
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}
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static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
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bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
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visit_type_bool(v, name, &value, errp);
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}
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static void cpu_add_multi_ext_prop(Object *cpu_obj,
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RISCVCPUMultiExtConfig *multi_cfg)
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{
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object_property_add(cpu_obj, multi_cfg->name, "bool",
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cpu_get_multi_ext_cfg,
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cpu_set_multi_ext_cfg,
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NULL, (void *)multi_cfg);
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/*
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* Set def val directly instead of using
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* object_property_set_bool() to save the set()
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* callback hash for user inputs.
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*/
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isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
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multi_cfg->enabled);
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}
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static void riscv_cpu_add_multiext_prop_array(Object *obj,
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RISCVCPUMultiExtConfig *array)
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{
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g_assert(array);
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for (Property *prop = array; prop && prop->name; prop++) {
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qdev_property_add_static(dev, prop);
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for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
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cpu_add_multi_ext_prop(obj, prop);
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}
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}
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@ -2034,11 +2093,11 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
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}
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static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
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Property *array)
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RISCVCPUMultiExtConfig *array)
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{
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g_assert(array);
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for (Property *prop = array; prop && prop->name; prop++) {
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for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
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riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
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}
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}
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@ -2073,8 +2132,6 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
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*/
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static void riscv_cpu_add_user_properties(Object *obj)
|
||||
{
|
||||
DeviceState *dev = DEVICE(obj);
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
riscv_add_satp_mode_properties(obj);
|
||||
|
||||
@ -2086,10 +2143,13 @@ static void riscv_cpu_add_user_properties(Object *obj)
|
||||
|
||||
riscv_cpu_add_misa_properties(obj);
|
||||
|
||||
riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
|
||||
riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
|
||||
riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
|
||||
riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
|
||||
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
|
||||
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
|
||||
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
|
||||
|
||||
for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
|
||||
qdev_property_add_static(DEVICE(obj), prop);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
@ -2100,7 +2160,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
|
||||
{
|
||||
RISCVCPU *cpu = RISCV_CPU(obj);
|
||||
CPURISCVState *env = &cpu->env;
|
||||
Property *prop;
|
||||
RISCVCPUMultiExtConfig *prop;
|
||||
|
||||
/* Enable RVG, RVJ and RVV that are disabled by default */
|
||||
set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user