OMAP STI/XTI console.
Add a dummy serial to receive the output from STI console (OMAP debugging/emulation interface). Add some more OMAP UART dummy registers. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4331 c046a42c-6fe2-441c-8c8c-71466251a162
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balrog
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4c54e87568
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54585ffec7
@ -330,6 +330,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
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/*
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* OMAP-24xx common IRQ numbers
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*/
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# define OMAP_INT_24XX_STI 4
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# define OMAP_INT_24XX_SYS_NIRQ 7
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# define OMAP_INT_24XX_L3_IRQ 10
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# define OMAP_INT_24XX_PRCM_MPU_IRQ 11
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20
hw/omap1.c
20
hw/omap1.c
@ -1987,6 +1987,8 @@ struct omap_uart_s {
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uint8_t syscontrol;
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uint8_t wkup;
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uint8_t cfps;
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uint8_t mdr[2];
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uint8_t scr;
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};
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void omap_uart_reset(struct omap_uart_s *s)
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@ -2015,6 +2017,14 @@ static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
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int offset = addr - s->base;
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switch (offset) {
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case 0x20: /* MDR1 */
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return s->mdr[0];
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case 0x24: /* MDR2 */
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return s->mdr[1];
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case 0x40: /* SCR */
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return s->scr;
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case 0x44: /* SSR */
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return 0x0;
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case 0x48: /* EBLR */
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return s->eblr;
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case 0x50: /* MVR */
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@ -2040,9 +2050,19 @@ static void omap_uart_write(void *opaque, target_phys_addr_t addr,
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int offset = addr - s->base;
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switch (offset) {
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case 0x20: /* MDR1 */
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s->mdr[0] = value & 0x7f;
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break;
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case 0x24: /* MDR2 */
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s->mdr[1] = value & 0xff;
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break;
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case 0x40: /* SCR */
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s->scr = value & 0xff;
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break;
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case 0x48: /* EBLR */
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s->eblr = value & 0xff;
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break;
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case 0x44: /* SSR */
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case 0x50: /* MVR */
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case 0x58: /* SYSS */
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OMAP_RO_REG(addr);
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196
hw/omap2.c
196
hw/omap2.c
@ -1419,6 +1419,196 @@ void omap_mcspi_attach(struct omap_mcspi_s *s,
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s->ch[chipselect].opaque = opaque;
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}
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/* STI/XTI (emulation interface) console - reverse engineered only */
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struct omap_sti_s {
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target_phys_addr_t base;
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target_phys_addr_t channel_base;
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qemu_irq irq;
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CharDriverState *chr;
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uint32_t sysconfig;
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uint32_t systest;
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uint32_t irqst;
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uint32_t irqen;
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uint32_t clkcontrol;
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uint32_t serial_config;
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};
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#define STI_TRACE_CONSOLE_CHANNEL 239
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#define STI_TRACE_CONTROL_CHANNEL 253
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static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
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{
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qemu_set_irq(s->irq, s->irqst & s->irqen);
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}
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static void omap_sti_reset(struct omap_sti_s *s)
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{
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s->sysconfig = 0;
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s->irqst = 0;
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s->irqen = 0;
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s->clkcontrol = 0;
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s->serial_config = 0;
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omap_sti_interrupt_update(s);
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}
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static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_sti_s *s = (struct omap_sti_s *) opaque;
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int offset = addr - s->base;
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switch (offset) {
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case 0x00: /* STI_REVISION */
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return 0x10;
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case 0x10: /* STI_SYSCONFIG */
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return s->sysconfig;
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case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
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return 0x00;
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case 0x18: /* STI_IRQSTATUS */
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return s->irqst;
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case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
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return s->irqen;
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case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
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case 0x28: /* STI_RX_DR / XTI_RXDATA */
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break;
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case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
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return s->clkcontrol;
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case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
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return s->serial_config;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_sti_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_sti_s *s = (struct omap_sti_s *) opaque;
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int offset = addr - s->base;
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switch (offset) {
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case 0x00: /* STI_REVISION */
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case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
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OMAP_RO_REG(addr);
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return;
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case 0x10: /* STI_SYSCONFIG */
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if (value & (1 << 1)) /* SOFTRESET */
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omap_sti_reset(s);
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s->sysconfig = value & 0xfe;
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break;
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case 0x18: /* STI_IRQSTATUS */
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s->irqst &= ~value;
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omap_sti_interrupt_update(s);
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break;
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case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
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s->irqen = value & 0xffff;
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omap_sti_interrupt_update(s);
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break;
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case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
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s->clkcontrol = value & 0xff;
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break;
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case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
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s->serial_config = value & 0xff;
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break;
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case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
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case 0x28: /* STI_RX_DR / XTI_RXDATA */
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static CPUReadMemoryFunc *omap_sti_readfn[] = {
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omap_badwidth_read32,
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omap_badwidth_read32,
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omap_sti_read,
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};
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static CPUWriteMemoryFunc *omap_sti_writefn[] = {
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omap_badwidth_write32,
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omap_badwidth_write32,
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omap_sti_write,
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};
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static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
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{
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_sti_s *s = (struct omap_sti_s *) opaque;
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int offset = addr - s->channel_base;
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int ch = offset >> 6;
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uint8_t byte = value;
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if (ch == STI_TRACE_CONTROL_CHANNEL) {
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/* Flush channel <i>value</i>. */
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qemu_chr_write(s->chr, "\r", 1);
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} else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
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if (value == 0xc0 || value == 0xc3) {
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/* Open channel <i>ch</i>. */
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} else if (value == 0x00)
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qemu_chr_write(s->chr, "\n", 1);
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else
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qemu_chr_write(s->chr, &byte, 1);
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}
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}
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static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
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omap_sti_fifo_read,
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omap_badwidth_read8,
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omap_badwidth_read8,
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};
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static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
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omap_sti_fifo_write,
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omap_badwidth_write8,
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omap_badwidth_write8,
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};
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struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
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target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
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CharDriverState *chr)
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{
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int iomemtype;
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struct omap_sti_s *s = (struct omap_sti_s *)
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qemu_mallocz(sizeof(struct omap_sti_s));
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s->irq = irq;
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omap_sti_reset(s);
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s->chr = chr ?: qemu_chr_open("null");
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iomemtype = cpu_register_io_memory(0, omap_sti_readfn,
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omap_sti_writefn, s);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
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omap_sti_fifo_writefn, s);
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s->channel_base = channel_base;
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cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype);
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return s;
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}
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/* L4 Interconnect */
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struct omap_target_agent_s {
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struct omap_l4_s *bus;
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@ -3674,6 +3864,11 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
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omap_findclk(s, "dss_l3_iclk"),
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omap_findclk(s, "dss_l4_iclk"));
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omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
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s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
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serial_hds[0] && serial_hds[1] && serial_hds[2] ?
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serial_hds[3] : 0);
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/* All register mappings (includin those not currenlty implemented):
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* SystemControlMod 48000000 - 48000fff
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* SystemControlL4 48001000 - 48001fff
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@ -3803,6 +3998,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
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* HDQ/1-wire Mod 480b2000 - 480b2fff
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* HDQ/1-wire L4 480b3000 - 480b3fff
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* MPU interrupt 480fe000 - 480fefff
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* STI channel base 54000000 - 5400ffff
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* IVA RAM 5c000000 - 5c01ffff
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* IVA ROM 5c020000 - 5c027fff
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* IMG_BUF_A 5c040000 - 5c040fff
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