xilinx_axienet: typedef XilinxAXIEnet struct
Typedef xilinx_axienets object state struct to shorten the repeated usages of struct XilinxAXIEnet. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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@ -306,6 +306,8 @@ struct TEMAC {
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void *parent;
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};
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typedef struct XilinxAXIEnet XilinxAXIEnet;
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struct XilinxAXIEnet {
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SysBusDevice busdev;
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MemoryRegion iomem;
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@ -365,37 +367,37 @@ struct XilinxAXIEnet {
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uint8_t *rxmem;
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};
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static void axienet_rx_reset(struct XilinxAXIEnet *s)
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static void axienet_rx_reset(XilinxAXIEnet *s)
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{
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s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
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}
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static void axienet_tx_reset(struct XilinxAXIEnet *s)
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static void axienet_tx_reset(XilinxAXIEnet *s)
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{
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s->tc = TC_JUM | TC_TX | TC_VLAN;
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}
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static inline int axienet_rx_resetting(struct XilinxAXIEnet *s)
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static inline int axienet_rx_resetting(XilinxAXIEnet *s)
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{
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return s->rcw[1] & RCW1_RST;
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}
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static inline int axienet_rx_enabled(struct XilinxAXIEnet *s)
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static inline int axienet_rx_enabled(XilinxAXIEnet *s)
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{
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return s->rcw[1] & RCW1_RX;
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}
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static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s)
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static inline int axienet_extmcf_enabled(XilinxAXIEnet *s)
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{
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return !!(s->regs[R_RAF] & RAF_EMCF_EN);
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}
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static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s)
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static inline int axienet_newfunc_enabled(XilinxAXIEnet *s)
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{
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return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
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}
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static void axienet_reset(struct XilinxAXIEnet *s)
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static void axienet_reset(XilinxAXIEnet *s)
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{
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axienet_rx_reset(s);
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axienet_tx_reset(s);
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@ -406,7 +408,7 @@ static void axienet_reset(struct XilinxAXIEnet *s)
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s->emmc = EMMC_LINKSPEED_100MB;
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}
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static void enet_update_irq(struct XilinxAXIEnet *s)
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static void enet_update_irq(XilinxAXIEnet *s)
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{
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s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
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qemu_set_irq(s->irq, !!s->regs[R_IP]);
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@ -414,7 +416,7 @@ static void enet_update_irq(struct XilinxAXIEnet *s)
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static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
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{
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struct XilinxAXIEnet *s = opaque;
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XilinxAXIEnet *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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@ -506,7 +508,7 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
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static void enet_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct XilinxAXIEnet *s = opaque;
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XilinxAXIEnet *s = opaque;
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struct TEMAC *t = &s->TEMAC;
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addr >>= 2;
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@ -620,7 +622,7 @@ static const MemoryRegionOps enet_ops = {
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static int eth_can_rx(NetClientState *nc)
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{
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struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
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XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
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/* RX enabled? */
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return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
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@ -643,7 +645,7 @@ static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
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static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
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XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
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static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
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0xff, 0xff, 0xff};
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static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
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@ -788,7 +790,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
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static void eth_cleanup(NetClientState *nc)
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{
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/* FIXME. */
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struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
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XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
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g_free(s->rxmem);
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g_free(s);
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}
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@ -796,7 +798,7 @@ static void eth_cleanup(NetClientState *nc)
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static void
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axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr)
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{
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struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
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XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
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/* TX enable ? */
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if (!(s->tc & TC_TX)) {
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@ -846,7 +848,7 @@ static NetClientInfo net_xilinx_enet_info = {
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static int xilinx_enet_init(SysBusDevice *dev)
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{
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struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
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XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
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sysbus_init_irq(dev, &s->irq);
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@ -871,7 +873,7 @@ static int xilinx_enet_init(SysBusDevice *dev)
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static void xilinx_enet_initfn(Object *obj)
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{
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struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
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XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
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Error *errp = NULL;
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object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
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@ -880,10 +882,10 @@ static void xilinx_enet_initfn(Object *obj)
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}
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static Property xilinx_enet_properties[] = {
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DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7),
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DEFINE_PROP_UINT32("rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000),
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DEFINE_PROP_UINT32("txmem", struct XilinxAXIEnet, c_txmem, 0x1000),
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DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf),
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DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7),
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DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
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DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
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DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -901,7 +903,7 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data)
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static const TypeInfo xilinx_enet_info = {
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.name = "xlnx.axi-ethernet",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct XilinxAXIEnet),
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.instance_size = sizeof(XilinxAXIEnet),
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.class_init = xilinx_enet_class_init,
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.instance_init = xilinx_enet_initfn,
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.interfaces = (InterfaceInfo[]) {
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