Merge branch 'for-upstream' of git://git.serverraum.org/git/mw/qemu-lm32
* 'for-upstream' of git://git.serverraum.org/git/mw/qemu-lm32: milkymist: new interrupt map milkymist_uart: support new core version lm32: add missing qemu_init_vcpu() call
This commit is contained in:
commit
53e621704c
@ -5,15 +5,14 @@
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#include "qdev-addr.h"
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#include "qdev-addr.h"
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static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
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static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
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qemu_irq rx_irq, qemu_irq tx_irq)
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qemu_irq irq)
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{
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{
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DeviceState *dev;
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DeviceState *dev;
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dev = qdev_create(NULL, "milkymist-uart");
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dev = qdev_create(NULL, "milkymist-uart");
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qdev_init_nofail(dev);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, rx_irq);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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sysbus_connect_irq(sysbus_from_qdev(dev), 1, tx_irq);
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return dev;
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return dev;
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}
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}
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@ -30,19 +30,53 @@
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enum {
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enum {
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R_RXTX = 0,
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R_RXTX = 0,
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R_DIV,
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R_DIV,
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R_STAT,
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R_CTRL,
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R_DBG,
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R_MAX
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R_MAX
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};
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};
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enum {
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STAT_THRE = (1<<0),
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STAT_RX_EVT = (1<<1),
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STAT_TX_EVT = (1<<2),
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};
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enum {
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CTRL_RX_IRQ_EN = (1<<0),
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CTRL_TX_IRQ_EN = (1<<1),
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CTRL_THRU_EN = (1<<2),
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};
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enum {
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DBG_BREAK_EN = (1<<0),
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};
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struct MilkymistUartState {
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struct MilkymistUartState {
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SysBusDevice busdev;
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SysBusDevice busdev;
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CharDriverState *chr;
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CharDriverState *chr;
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qemu_irq rx_irq;
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qemu_irq irq;
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qemu_irq tx_irq;
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uint32_t regs[R_MAX];
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uint32_t regs[R_MAX];
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};
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};
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typedef struct MilkymistUartState MilkymistUartState;
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typedef struct MilkymistUartState MilkymistUartState;
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static void uart_update_irq(MilkymistUartState *s)
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{
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int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
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int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
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int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
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int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
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if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
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trace_milkymist_uart_raise_irq();
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qemu_irq_raise(s->irq);
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} else {
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trace_milkymist_uart_lower_irq();
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qemu_irq_lower(s->irq);
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}
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}
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static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
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static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
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{
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{
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MilkymistUartState *s = opaque;
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MilkymistUartState *s = opaque;
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@ -51,7 +85,12 @@ static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
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addr >>= 2;
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addr >>= 2;
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switch (addr) {
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switch (addr) {
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case R_RXTX:
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case R_RXTX:
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r = s->regs[addr];
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break;
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case R_DIV:
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case R_DIV:
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case R_STAT:
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case R_CTRL:
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case R_DBG:
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r = s->regs[addr];
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r = s->regs[addr];
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break;
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break;
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@ -79,18 +118,26 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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if (s->chr) {
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if (s->chr) {
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qemu_chr_fe_write(s->chr, &ch, 1);
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qemu_chr_fe_write(s->chr, &ch, 1);
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}
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}
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trace_milkymist_uart_pulse_irq_tx();
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s->regs[R_STAT] |= STAT_TX_EVT;
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qemu_irq_pulse(s->tx_irq);
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break;
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break;
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case R_DIV:
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case R_DIV:
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case R_CTRL:
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case R_DBG:
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s->regs[addr] = value;
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s->regs[addr] = value;
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break;
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break;
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case R_STAT:
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/* write one to clear bits */
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s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
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break;
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default:
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default:
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error_report("milkymist_uart: write access to unknown register 0x"
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error_report("milkymist_uart: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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TARGET_FMT_plx, addr << 2);
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break;
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break;
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}
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}
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uart_update_irq(s);
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}
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}
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static CPUReadMemoryFunc * const uart_read_fn[] = {
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static CPUReadMemoryFunc * const uart_read_fn[] = {
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@ -109,14 +156,19 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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{
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MilkymistUartState *s = opaque;
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MilkymistUartState *s = opaque;
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assert(!(s->regs[R_STAT] & STAT_RX_EVT));
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s->regs[R_STAT] |= STAT_RX_EVT;
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s->regs[R_RXTX] = *buf;
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s->regs[R_RXTX] = *buf;
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trace_milkymist_uart_pulse_irq_rx();
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qemu_irq_pulse(s->rx_irq);
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uart_update_irq(s);
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}
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}
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static int uart_can_rx(void *opaque)
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static int uart_can_rx(void *opaque)
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{
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{
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return 1;
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MilkymistUartState *s = opaque;
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return !(s->regs[R_STAT] & STAT_RX_EVT);
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}
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}
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static void uart_event(void *opaque, int event)
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static void uart_event(void *opaque, int event)
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@ -131,6 +183,9 @@ static void milkymist_uart_reset(DeviceState *d)
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for (i = 0; i < R_MAX; i++) {
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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s->regs[i] = 0;
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}
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}
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/* THRE is always set */
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s->regs[R_STAT] = STAT_THRE;
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}
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}
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static int milkymist_uart_init(SysBusDevice *dev)
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static int milkymist_uart_init(SysBusDevice *dev)
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@ -138,8 +193,7 @@ static int milkymist_uart_init(SysBusDevice *dev)
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MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
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MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
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int uart_regs;
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int uart_regs;
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sysbus_init_irq(dev, &s->rx_irq);
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(dev, &s->tx_irq);
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uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
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uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
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DEVICE_NATIVE_ENDIAN);
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DEVICE_NATIVE_ENDIAN);
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@ -146,17 +146,17 @@ milkymist_init(ram_addr_t ram_size_not_used,
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exit(1);
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exit(1);
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}
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}
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milkymist_uart_create(0x60000000, irq[0], irq[1]);
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milkymist_uart_create(0x60000000, irq[0]);
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milkymist_sysctl_create(0x60001000, irq[2], irq[3], irq[4],
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milkymist_sysctl_create(0x60001000, irq[1], irq[2], irq[3],
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80000000, 0x10014d31, 0x0000041f, 0x00000001);
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80000000, 0x10014d31, 0x0000041f, 0x00000001);
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milkymist_hpdmc_create(0x60002000);
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milkymist_hpdmc_create(0x60002000);
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milkymist_vgafb_create(0x60003000, 0x40000000, 0x0fffffff);
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milkymist_vgafb_create(0x60003000, 0x40000000, 0x0fffffff);
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milkymist_memcard_create(0x60004000);
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milkymist_memcard_create(0x60004000);
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milkymist_ac97_create(0x60005000, irq[5], irq[6], irq[7], irq[8]);
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milkymist_ac97_create(0x60005000, irq[4], irq[5], irq[6], irq[7]);
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milkymist_pfpu_create(0x60006000, irq[9]);
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milkymist_pfpu_create(0x60006000, irq[8]);
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milkymist_tmu2_create(0x60007000, irq[10]);
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milkymist_tmu2_create(0x60007000, irq[9]);
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milkymist_minimac2_create(0x60008000, 0x30000000, irq[11], irq[12]);
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milkymist_minimac2_create(0x60008000, 0x30000000, irq[10], irq[11]);
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milkymist_softusb_create(0x6000f000, irq[17],
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milkymist_softusb_create(0x6000f000, irq[15],
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0x20000000, 0x1000, 0x20020000, 0x2000);
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0x20000000, 0x1000, 0x20020000, 0x2000);
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/* make sure juart isn't the first chardev */
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/* make sure juart isn't the first chardev */
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@ -218,6 +218,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
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cpu_exec_init(env);
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cpu_exec_init(env);
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cpu_reset(env);
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cpu_reset(env);
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qemu_init_vcpu(env);
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if (!tcg_initialized) {
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if (!tcg_initialized) {
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tcg_initialized = 1;
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tcg_initialized = 1;
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@ -445,8 +445,8 @@ milkymist_tmu2_pulse_irq(void) "Pulse IRQ"
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# hw/milkymist-uart.c
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# hw/milkymist-uart.c
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milkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
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milkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
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milkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
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milkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
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milkymist_uart_pulse_irq_rx(void) "Pulse IRQ RX"
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milkymist_uart_raise_irq(void) "Raise IRQ"
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milkymist_uart_pulse_irq_tx(void) "Pulse IRQ TX"
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milkymist_uart_lower_irq(void) "Lower IRQ"
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# hw/milkymist-vgafb.c
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# hw/milkymist-vgafb.c
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milkymist_vgafb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
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milkymist_vgafb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
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