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hw/misc/mips_itu: Make MIPSITUState target agnostic

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When prototyping a heterogenous machine including the ITU,
we get:

  include/hw/misc/mips_itu.h:76:5: error: unknown type name 'MIPSCPU'
      MIPSCPU *cpu0;
      ^

MIPSCPU is declared in the target specific "cpu.h" header,
but we don't want to include it, because "cpu.h" is target
specific and its inclusion taints all files including
"mips_itu.h", which become target specific too. We can
however use the 'ArchCPU *' type in the public header.
By keeping the TYPE_MIPS_CPU QOM type check in the link
property declaration, QOM core code will still check the
property is a correct MIPS CPU.

TYPE_MIPS_ITU is still built per-(MIPS)target, but its header
can now be included by other targets.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231009171443.12145-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-09-18 07:25:49 +02:00
parent db646e830e
commit 53af33a5b4
2 changed files with 3 additions and 3 deletions
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4
hw/misc/mips_itu.c
View File

@ -532,7 +532,7 @@ static void mips_itu_realize(DeviceState *dev, Error **errp)
return;
}
env = &s->cpu0->env;
env = &MIPS_CPU(s->cpu0)->env;
if (env->saarp) {
s->saar = env->CP0_SAAR;
}
@ -563,7 +563,7 @@ static Property mips_itu_properties[] = {
ITC_FIFO_NUM_MAX),
DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,
ITC_SEMAPH_NUM_MAX),
DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU *),
DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *),
DEFINE_PROP_END_OF_LIST(),
};

2
include/hw/misc/mips_itu.h
View File

@ -73,7 +73,7 @@ struct MIPSITUState {
/* SAAR */
uint64_t *saar;
MIPSCPU *cpu0;
ArchCPU *cpu0;
};
/* Get ITC Configuration Tag memory region. */