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target/arm: Don't set syndrome ISS for loads and stores with writeback

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The architecture requires that for faults on loads and stores which
do writeback, the syndrome information does not have the ISS
instruction syndrome information (i.e. ISV is 0).  We got this wrong
for the load and store instructions covered by disas_ldst_reg_imm9().
Calculate iss_valid correctly so that if the insn is a writeback one
it is false.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-07-15 13:33:23 +01:00
parent 99638ba9d8
commit 53ae2fdef1
1 changed files with 3 additions and 1 deletions
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4
target/arm/translate-a64.c
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@ -3138,7 +3138,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
bool is_store = false;
bool is_extended = false;
bool is_unpriv = (idx == 2);
bool iss_valid = !is_vector;
bool iss_valid;
bool post_index;
bool writeback;
int memidx;
@ -3191,6 +3191,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
g_assert_not_reached();
}
iss_valid = !is_vector && !writeback;
if (rn == 31) {
gen_check_sp_alignment(s);
}