mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs'

Browse Source 
Follow the naming used by other files in target/i386/.

No functional changes.

Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231020111136.44401-3-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-10-20 13:02:16 +02:00
parent 89c02195c9
commit 5366a0644f
1 changed files with 46 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
target/i386/hvf/x86_emu.c
View File

@ -45,7 +45,7 @@
#include "vmcs.h" #include "vmcs.h"
#include "vmx.h" #include "vmx.h"
void hvf_handle_io(CPUState *cpu, uint16_t port, void *data, void hvf_handle_io(CPUState *cs, uint16_t port, void *data,
int direction, int size, uint32_t count); int direction, int size, uint32_t count);
#define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \ #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
@ -666,13 +666,13 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
void simulate_rdmsr(CPUX86State *env) void simulate_rdmsr(CPUX86State *env)
{ {
X86CPU *x86_cpu = env_archcpu(env); X86CPU *x86_cpu = env_archcpu(env);
CPUState *cpu = env_cpu(env); CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env); uint32_t msr = ECX(env);
uint64_t val = 0; uint64_t val = 0;
switch (msr) { switch (msr) {
case MSR_IA32_TSC: case MSR_IA32_TSC:
val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break; break;
case MSR_IA32_APICBASE: case MSR_IA32_APICBASE:
val = cpu_get_apic_base(x86_cpu->apic_state); val = cpu_get_apic_base(x86_cpu->apic_state);
@ -681,16 +681,16 @@ void simulate_rdmsr(CPUX86State *env)
val = x86_cpu->ucode_rev; val = x86_cpu->ucode_rev;
break; break;
case MSR_EFER: case MSR_EFER:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER); val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
break; break;
case MSR_FSBASE: case MSR_FSBASE:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE); val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE);
break; break;
case MSR_GSBASE: case MSR_GSBASE:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE); val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE);
break; break;
case MSR_KERNELGSBASE: case MSR_KERNELGSBASE:
val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE); val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE);
break; break;
case MSR_STAR: case MSR_STAR:
abort(); abort();
@ -745,8 +745,8 @@ void simulate_rdmsr(CPUX86State *env)
val = env->mtrr_deftype; val = env->mtrr_deftype;
break; break;
case MSR_CORE_THREAD_COUNT: case MSR_CORE_THREAD_COUNT:
val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */ val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */ val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
break; break;
default: default:
/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
@ -767,7 +767,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
void simulate_wrmsr(CPUX86State *env) void simulate_wrmsr(CPUX86State *env)
{ {
X86CPU *x86_cpu = env_archcpu(env); X86CPU *x86_cpu = env_archcpu(env);
CPUState *cpu = env_cpu(env); CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env); uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@ -778,13 +778,13 @@ void simulate_wrmsr(CPUX86State *env)
cpu_set_apic_base(x86_cpu->apic_state, data); cpu_set_apic_base(x86_cpu->apic_state, data);
break; break;
case MSR_FSBASE: case MSR_FSBASE:
wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
break; break;
case MSR_GSBASE: case MSR_GSBASE:
wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data); wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data);
break; break;
case MSR_KERNELGSBASE: case MSR_KERNELGSBASE:
wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data); wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data);
break; break;
case MSR_STAR: case MSR_STAR:
abort(); abort();
@ -796,10 +796,10 @@ void simulate_wrmsr(CPUX86State *env)
abort(); abort();
break; break;
case MSR_EFER: case MSR_EFER:
/*printf("new efer %llx\n", EFER(cpu));*/ /*printf("new efer %llx\n", EFER(cs));*/
wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data); wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data);
if (data & MSR_EFER_NXE) { if (data & MSR_EFER_NXE) {
hv_vcpu_invalidate_tlb(cpu->accel->fd); hv_vcpu_invalidate_tlb(cs->accel->fd);
} }
break; break;
case MSR_MTRRphysBase(0): case MSR_MTRRphysBase(0):
@ -848,9 +848,9 @@ void simulate_wrmsr(CPUX86State *env)
/* Related to support known hypervisor interface */ /* Related to support known hypervisor interface */
/* if (g_hypervisor_iface) /* if (g_hypervisor_iface)
g_hypervisor_iface->wrmsr_handler(cpu, msr, data); g_hypervisor_iface->wrmsr_handler(cs, msr, data);
printf("write msr %llx\n", RCX(cpu));*/ printf("write msr %llx\n", RCX(cs));*/
} }
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
@ -1417,56 +1417,56 @@ static void init_cmd_handler()
} }
} }
void load_regs(CPUState *cpu) void load_regs(CPUState *cs)
{ {
X86CPU *x86_cpu = X86_CPU(cpu); X86CPU *x86_cpu = X86_CPU(cs);
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
int i = 0; int i = 0;
RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX); RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX); RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX); RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX); RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI); RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI); RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP); RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP); RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
for (i = 8; i < 16; i++) { for (i = 8; i < 16; i++) {
RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i); RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
} }
env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS); env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
rflags_to_lflags(env); rflags_to_lflags(env);
env->eip = rreg(cpu->accel->fd, HV_X86_RIP); env->eip = rreg(cs->accel->fd, HV_X86_RIP);
} }
void store_regs(CPUState *cpu) void store_regs(CPUState *cs)
{ {
X86CPU *x86_cpu = X86_CPU(cpu); X86CPU *x86_cpu = X86_CPU(cs);
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
int i = 0; int i = 0;
wreg(cpu->accel->fd, HV_X86_RAX, RAX(env)); wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
wreg(cpu->accel->fd, HV_X86_RBX, RBX(env)); wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
wreg(cpu->accel->fd, HV_X86_RCX, RCX(env)); wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
wreg(cpu->accel->fd, HV_X86_RDX, RDX(env)); wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
wreg(cpu->accel->fd, HV_X86_RSI, RSI(env)); wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
wreg(cpu->accel->fd, HV_X86_RDI, RDI(env)); wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
wreg(cpu->accel->fd, HV_X86_RBP, RBP(env)); wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
wreg(cpu->accel->fd, HV_X86_RSP, RSP(env)); wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
for (i = 8; i < 16; i++) { for (i = 8; i < 16; i++) {
wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i)); wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
} }
lflags_to_rflags(env); lflags_to_rflags(env);
wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags); wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
macvm_set_rip(cpu, env->eip); macvm_set_rip(cs, env->eip);
} }
bool exec_instruction(CPUX86State *env, struct x86_decode *ins) bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
{ {
/*if (hvf_vcpu_id(cpu)) /*if (hvf_vcpu_id(cs))
printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip, printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cs), env->eip,
decode_cmd_to_string(ins->cmd));*/ decode_cmd_to_string(ins->cmd));*/
if (!_cmd_handler[ins->cmd].handler) { if (!_cmd_handler[ins->cmd].handler) {