arm/aspeed: actually check RAM size
It's supposed that SOC will check if "-m" provided RAM size is valid by setting "ram-size" property and then board would read back valid (possibly corrected value) to map RAM MemoryReging with valid size. It isn't doing so, since check is called only indirectly from aspeed_sdmc_reset()->asc->compute_conf() or much later when guest writes to configuration register. So depending on "-m" value QEMU end-ups with a warning and an invalid MemoryRegion size allocated and mapped. (examples: -M ast2500-evb -m 1M 0000000080000000-000000017ffffffe (prio 0, i/o): aspeed-ram-container 0000000080000000-00000000800fffff (prio 0, ram): ram 0000000080100000-00000000bfffffff (prio 0, i/o): max_ram -M ast2500-evb -m 3G 0000000080000000-000000017ffffffe (prio 0, i/o): aspeed-ram-container 0000000080000000-000000013fffffff (prio 0, ram): ram [DETECTED OVERFLOW!] 0000000140000000-00000000bfffffff (prio 0, i/o): max_ram ) On top of that sdmc falls back and reports to guest "default" size, it thinks machine should have. This patch makes ram-size check actually work and changes behavior from a warning later on during machine reset to error_fatal at the moment SOC.ram-size is set so user will have to fix RAM size on CLI to start machine. It also gets out of the way mutable ram-size logic, so we could consolidate RAM allocation logic around pre-allocated hostmem backend (supplied by user or auto created by generic machine code depending on supplied -m/mem-path/mem-prealloc options. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200219160953.13771-10-imammedo@redhat.com>
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@ -204,8 +204,12 @@ static void aspeed_machine_init(MachineState *machine)
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sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
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sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
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/*
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* This will error out if isize is not supported by memory controller.
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*/
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object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
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object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
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&error_abort);
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&error_fatal);
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object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1",
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object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1",
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&error_abort);
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&error_abort);
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object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2",
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object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2",
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@ -228,13 +232,6 @@ static void aspeed_machine_init(MachineState *machine)
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object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
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object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
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&error_abort);
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&error_abort);
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/*
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* Allocate RAM after the memory controller has checked the size
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* was valid. If not, a default value is used.
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*/
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ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size",
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&error_abort);
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memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
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memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
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memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
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memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
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memory_region_add_subregion(get_system_memory(),
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memory_region_add_subregion(get_system_memory(),
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@ -17,6 +17,9 @@
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#include "migration/vmstate.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "trace.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qapi/visitor.h"
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/* Protection Key Register */
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/* Protection Key Register */
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#define R_PROT (0x00 / 4)
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#define R_PROT (0x00 / 4)
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@ -160,14 +163,9 @@ static int ast2400_rambits(AspeedSDMCState *s)
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case 512:
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case 512:
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return ASPEED_SDMC_DRAM_512MB;
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return ASPEED_SDMC_DRAM_512MB;
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default:
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default:
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g_assert_not_reached();
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break;
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break;
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}
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}
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/* use a common default */
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warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
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s->ram_size);
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s->ram_size = 256 << 20;
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return ASPEED_SDMC_DRAM_256MB;
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}
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}
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static int ast2500_rambits(AspeedSDMCState *s)
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static int ast2500_rambits(AspeedSDMCState *s)
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@ -182,14 +180,9 @@ static int ast2500_rambits(AspeedSDMCState *s)
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case 1024:
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case 1024:
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return ASPEED_SDMC_AST2500_1024MB;
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return ASPEED_SDMC_AST2500_1024MB;
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default:
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default:
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g_assert_not_reached();
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break;
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break;
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}
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}
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/* use a common default */
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warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
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s->ram_size);
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s->ram_size = 512 << 20;
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return ASPEED_SDMC_AST2500_512MB;
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}
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}
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static int ast2600_rambits(AspeedSDMCState *s)
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static int ast2600_rambits(AspeedSDMCState *s)
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@ -204,14 +197,9 @@ static int ast2600_rambits(AspeedSDMCState *s)
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case 2048:
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case 2048:
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return ASPEED_SDMC_AST2600_2048MB;
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return ASPEED_SDMC_AST2600_2048MB;
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default:
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default:
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g_assert_not_reached();
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break;
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break;
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}
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}
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/* use a common default */
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warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 1024M",
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s->ram_size);
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s->ram_size = 1024 << 20;
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return ASPEED_SDMC_AST2600_1024MB;
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}
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}
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static void aspeed_sdmc_reset(DeviceState *dev)
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static void aspeed_sdmc_reset(DeviceState *dev)
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@ -225,6 +213,51 @@ static void aspeed_sdmc_reset(DeviceState *dev)
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s->regs[R_CONF] = asc->compute_conf(s, 0);
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s->regs[R_CONF] = asc->compute_conf(s, 0);
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}
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}
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static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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AspeedSDMCState *s = ASPEED_SDMC(obj);
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int64_t value = s->ram_size;
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visit_type_int(v, name, &value, errp);
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}
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static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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int i;
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char *sz;
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int64_t value;
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Error *local_err = NULL;
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AspeedSDMCState *s = ASPEED_SDMC(obj);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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visit_type_int(v, name, &value, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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for (i = 0; asc->valid_ram_sizes[i]; i++) {
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if (value == asc->valid_ram_sizes[i]) {
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s->ram_size = value;
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return;
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}
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}
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sz = size_to_str(value);
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error_setg(&local_err, "Invalid RAM size %s", sz);
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g_free(sz);
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error_propagate(errp, local_err);
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}
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static void aspeed_sdmc_initfn(Object *obj)
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{
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object_property_add(obj, "ram-size", "int",
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aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
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NULL, NULL, NULL);
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}
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static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
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static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
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{
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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@ -249,7 +282,6 @@ static const VMStateDescription vmstate_aspeed_sdmc = {
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};
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};
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static Property aspeed_sdmc_properties[] = {
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static Property aspeed_sdmc_properties[] = {
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DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
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DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
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DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -268,6 +300,7 @@ static const TypeInfo aspeed_sdmc_info = {
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.name = TYPE_ASPEED_SDMC,
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.name = TYPE_ASPEED_SDMC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSDMCState),
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.instance_size = sizeof(AspeedSDMCState),
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.instance_init = aspeed_sdmc_initfn,
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.class_init = aspeed_sdmc_class_init,
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.class_init = aspeed_sdmc_class_init,
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.class_size = sizeof(AspeedSDMCClass),
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.class_size = sizeof(AspeedSDMCClass),
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.abstract = true,
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.abstract = true,
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@ -298,6 +331,9 @@ static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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s->regs[reg] = data;
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s->regs[reg] = data;
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}
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}
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static const uint64_t
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aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
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static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
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static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -307,6 +343,7 @@ static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
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asc->max_ram_size = 512 << 20;
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asc->max_ram_size = 512 << 20;
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asc->compute_conf = aspeed_2400_sdmc_compute_conf;
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asc->compute_conf = aspeed_2400_sdmc_compute_conf;
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asc->write = aspeed_2400_sdmc_write;
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asc->write = aspeed_2400_sdmc_write;
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asc->valid_ram_sizes = aspeed_2400_ram_sizes;
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}
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}
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static const TypeInfo aspeed_2400_sdmc_info = {
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static const TypeInfo aspeed_2400_sdmc_info = {
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@ -351,6 +388,9 @@ static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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s->regs[reg] = data;
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s->regs[reg] = data;
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}
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}
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static const uint64_t
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aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
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static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
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static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -360,6 +400,7 @@ static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
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asc->max_ram_size = 1024 << 20;
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asc->max_ram_size = 1024 << 20;
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asc->compute_conf = aspeed_2500_sdmc_compute_conf;
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asc->compute_conf = aspeed_2500_sdmc_compute_conf;
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asc->write = aspeed_2500_sdmc_write;
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asc->write = aspeed_2500_sdmc_write;
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asc->valid_ram_sizes = aspeed_2500_ram_sizes;
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}
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}
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static const TypeInfo aspeed_2500_sdmc_info = {
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static const TypeInfo aspeed_2500_sdmc_info = {
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@ -404,6 +445,9 @@ static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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s->regs[reg] = data;
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s->regs[reg] = data;
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}
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}
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static const uint64_t
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aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
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static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
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static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -413,6 +457,7 @@ static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
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asc->max_ram_size = 2048 << 20;
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asc->max_ram_size = 2048 << 20;
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asc->compute_conf = aspeed_2600_sdmc_compute_conf;
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asc->compute_conf = aspeed_2600_sdmc_compute_conf;
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asc->write = aspeed_2600_sdmc_write;
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asc->write = aspeed_2600_sdmc_write;
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asc->valid_ram_sizes = aspeed_2600_ram_sizes;
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}
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}
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static const TypeInfo aspeed_2600_sdmc_info = {
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static const TypeInfo aspeed_2600_sdmc_info = {
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@ -40,6 +40,7 @@ typedef struct AspeedSDMCClass {
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SysBusDeviceClass parent_class;
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SysBusDeviceClass parent_class;
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uint64_t max_ram_size;
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uint64_t max_ram_size;
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const uint64_t *valid_ram_sizes;
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uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
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uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
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void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
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void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
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} AspeedSDMCClass;
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} AspeedSDMCClass;
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