hw/ide/piix: Refactor pci_piix_init_ports as pci_piix_init_bus per bus
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230215112712.23110-21-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -121,7 +121,7 @@ static void piix_ide_reset(DeviceState *dev)
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pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
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}
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static bool pci_piix_init_ports(PCIIDEState *d, Error **errp)
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static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
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{
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static const struct {
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int iobase;
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@ -131,24 +131,21 @@ static bool pci_piix_init_ports(PCIIDEState *d, Error **errp)
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{0x1f0, 0x3f6, 14},
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{0x170, 0x376, 15},
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};
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int i, ret;
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int ret;
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for (i = 0; i < 2; i++) {
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ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
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ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
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port_info[i].iobase2);
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if (ret) {
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error_setg_errno(errp, -ret, "Failed to realize %s port %u",
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object_get_typename(OBJECT(d)), i);
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return false;
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}
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ide_bus_init_output_irq(&d->bus[i],
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isa_get_irq(NULL, port_info[i].isairq));
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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d->bmdma[i].bus = &d->bus[i];
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ide_bus_register_restart_cb(&d->bus[i]);
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ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
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ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
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port_info[i].iobase2);
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if (ret) {
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error_setg_errno(errp, -ret, "Failed to realize %s port %u",
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object_get_typename(OBJECT(d)), i);
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return false;
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}
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ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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d->bmdma[i].bus = &d->bus[i];
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ide_bus_register_restart_cb(&d->bus[i]);
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return true;
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}
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@ -165,8 +162,10 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
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vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
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if (!pci_piix_init_ports(d, errp)) {
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return;
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for (unsigned i = 0; i < 2; i++) {
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if (!pci_piix_init_bus(d, i, errp)) {
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return;
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}
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}
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}
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