tcg/i386: Introduce prepare_host_addr
Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
83ecdb18eb
commit
530074c6c1
@ -1802,135 +1802,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
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[MO_BEUQ] = helper_be_stq_mmu,
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};
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/* Perform the TLB load and compare.
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Inputs:
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ADDRLO and ADDRHI contain the low and high part of the address.
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MEM_INDEX and S_BITS are the memory context and log2 size of the load.
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WHICH is the offset into the CPUTLBEntry structure of the slot to read.
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This should be offsetof addr_read or addr_write.
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Outputs:
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LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses)
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positions of the displacements of forward jumps to the TLB miss case.
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Second argument register is loaded with the low part of the address.
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In the TLB hit case, it has been adjusted as indicated by the TLB
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and so is a host address. In the TLB miss case, it continues to
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hold a guest address.
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First argument register is clobbered. */
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static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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int mem_index, MemOp opc,
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tcg_insn_unit **label_ptr, int which)
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{
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TCGType ttype = TCG_TYPE_I32;
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TCGType tlbtype = TCG_TYPE_I32;
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int trexw = 0, hrexw = 0, tlbrexw = 0;
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unsigned a_bits = get_alignment_bits(opc);
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unsigned s_bits = opc & MO_SIZE;
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unsigned a_mask = (1 << a_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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target_ulong tlb_mask;
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if (TCG_TARGET_REG_BITS == 64) {
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if (TARGET_LONG_BITS == 64) {
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ttype = TCG_TYPE_I64;
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trexw = P_REXW;
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}
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if (TCG_TYPE_PTR == TCG_TYPE_I64) {
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hrexw = P_REXW;
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if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) {
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tlbtype = TCG_TYPE_I64;
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tlbrexw = P_REXW;
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}
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}
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}
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tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
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tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
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TLB_MASK_TABLE_OFS(mem_index) +
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offsetof(CPUTLBDescFast, mask));
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tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
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TLB_MASK_TABLE_OFS(mem_index) +
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offsetof(CPUTLBDescFast, table));
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/* If the required alignment is at least as large as the access, simply
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copy the address and mask. For lesser alignments, check that we don't
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cross pages for the complete access. */
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if (a_bits >= s_bits) {
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tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
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} else {
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tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
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addrlo, s_mask - a_mask);
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}
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tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
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tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
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/* cmp 0(TCG_REG_L0), TCG_REG_L1 */
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tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
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TCG_REG_L1, TCG_REG_L0, which);
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/* Prepare for both the fast path add of the tlb addend, and the slow
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path function argument setup. */
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tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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label_ptr[0] = s->code_ptr;
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s->code_ptr += 4;
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if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
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/* cmp 4(TCG_REG_L0), addrhi */
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tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, which + 4);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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label_ptr[1] = s->code_ptr;
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s->code_ptr += 4;
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}
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/* TLB Hit. */
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/* add addend(TCG_REG_L0), TCG_REG_L1 */
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tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L1, TCG_REG_L0,
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offsetof(CPUTLBEntry, addend));
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}
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/*
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* Record the context of a call to the out of line helper code for the slow path
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* for a load or store, so that we can later generate the correct helper code
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*/
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static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
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TCGType type, MemOpIdx oi,
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TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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tcg_insn_unit *raddr,
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tcg_insn_unit **label_ptr)
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{
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->oi = oi;
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label->type = type;
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label->datalo_reg = datalo;
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label->datahi_reg = datahi;
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label->addrlo_reg = addrlo;
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label->addrhi_reg = addrhi;
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label->raddr = tcg_splitwx_to_rx(raddr);
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label->label_ptr[0] = label_ptr[0];
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if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
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label->label_ptr[1] = label_ptr[1];
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}
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}
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/*
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* Generate code for the slow path for a load at the end of block
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*/
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@ -2061,27 +1932,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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return true;
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}
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#else
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static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
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TCGReg addrhi, unsigned a_bits)
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{
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unsigned a_mask = (1 << a_bits) - 1;
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TCGLabelQemuLdst *label;
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tcg_out_testi(s, addrlo, a_mask);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->addrlo_reg = addrlo;
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label->addrhi_reg = addrhi;
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label->raddr = tcg_splitwx_to_rx(s->code_ptr + 4);
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label->label_ptr[0] = s->code_ptr;
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s->code_ptr += 4;
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}
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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{
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/* resolve label address */
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@ -2159,6 +2009,135 @@ static inline int setup_guest_base_seg(void)
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#endif /* setup_guest_base_seg */
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#endif /* SOFTMMU */
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/*
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* For softmmu, perform the TLB load and compare.
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* For useronly, perform any required alignment tests.
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* In both cases, return a TCGLabelQemuLdst structure if the slow path
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* is required and fill in @h with the host address for the fast path.
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*/
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static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, bool is_ld)
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{
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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unsigned a_bits = get_alignment_bits(opc);
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unsigned a_mask = (1 << a_bits) - 1;
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#ifdef CONFIG_SOFTMMU
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int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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TCGType ttype = TCG_TYPE_I32;
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TCGType tlbtype = TCG_TYPE_I32;
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int trexw = 0, hrexw = 0, tlbrexw = 0;
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unsigned mem_index = get_mmuidx(oi);
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unsigned s_bits = opc & MO_SIZE;
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unsigned s_mask = (1 << s_bits) - 1;
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target_ulong tlb_mask;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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if (TCG_TARGET_REG_BITS == 64) {
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if (TARGET_LONG_BITS == 64) {
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ttype = TCG_TYPE_I64;
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trexw = P_REXW;
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}
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if (TCG_TYPE_PTR == TCG_TYPE_I64) {
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hrexw = P_REXW;
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if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) {
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tlbtype = TCG_TYPE_I64;
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tlbrexw = P_REXW;
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}
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}
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}
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tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
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tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
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TLB_MASK_TABLE_OFS(mem_index) +
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offsetof(CPUTLBDescFast, mask));
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tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
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TLB_MASK_TABLE_OFS(mem_index) +
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offsetof(CPUTLBDescFast, table));
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/*
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* If the required alignment is at least as large as the access, simply
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* copy the address and mask. For lesser alignments, check that we don't
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* cross pages for the complete access.
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*/
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if (a_bits >= s_bits) {
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tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
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} else {
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tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
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addrlo, s_mask - a_mask);
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}
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tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
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tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
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/* cmp 0(TCG_REG_L0), TCG_REG_L1 */
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tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
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TCG_REG_L1, TCG_REG_L0, cmp_ofs);
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/*
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* Prepare for both the fast path add of the tlb addend, and the slow
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* path function argument setup.
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*/
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*h = (HostAddress) {
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.base = TCG_REG_L1,
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.index = -1
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};
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tcg_out_mov(s, ttype, h->base, addrlo);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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ldst->label_ptr[0] = s->code_ptr;
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s->code_ptr += 4;
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if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
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/* cmp 4(TCG_REG_L0), addrhi */
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tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs + 4);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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ldst->label_ptr[1] = s->code_ptr;
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s->code_ptr += 4;
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}
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/* TLB Hit. */
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/* add addend(TCG_REG_L0), TCG_REG_L1 */
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tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, h->base, TCG_REG_L0,
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offsetof(CPUTLBEntry, addend));
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#else
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if (a_bits) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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tcg_out_testi(s, addrlo, a_mask);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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ldst->label_ptr[0] = s->code_ptr;
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s->code_ptr += 4;
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}
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*h = x86_guest_base;
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h->base = addrlo;
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#endif
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return ldst;
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}
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static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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HostAddress h, TCGType type, MemOp memop)
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{
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@ -2258,35 +2237,18 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[2];
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ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
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tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi));
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tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc,
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label_ptr, offsetof(CPUTLBEntry, addr_read));
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/* TLB Hit. */
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h.base = TCG_REG_L1;
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h.index = -1;
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h.ofs = 0;
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h.seg = 0;
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tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc);
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/* Record the current context of a load into ldst label */
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add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi,
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addrlo, addrhi, s->code_ptr, label_ptr);
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#else
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
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if (ldst) {
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ldst->type = data_type;
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ldst->datalo_reg = datalo;
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ldst->datahi_reg = datahi;
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ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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h = x86_guest_base;
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h.base = addrlo;
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tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc);
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#endif
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}
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static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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@ -2345,36 +2307,18 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[2];
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ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
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tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi));
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tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc,
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label_ptr, offsetof(CPUTLBEntry, addr_write));
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/* TLB Hit. */
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h.base = TCG_REG_L1;
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h.index = -1;
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h.ofs = 0;
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h.seg = 0;
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tcg_out_qemu_st_direct(s, datalo, datahi, h, opc);
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/* Record the current context of a store into ldst label */
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add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi,
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addrlo, addrhi, s->code_ptr, label_ptr);
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#else
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
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if (ldst) {
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ldst->type = data_type;
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ldst->datalo_reg = datalo;
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ldst->datahi_reg = datahi;
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ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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h = x86_guest_base;
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h.base = addrlo;
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tcg_out_qemu_st_direct(s, datalo, datahi, h, opc);
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#endif
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}
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static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
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