s390x/tcg: simplify machine check handling
We currently only support CRW machine checks. This is a preparation for real floating interrupt support. Get rid of the queue and handle it via the bit INTERRUPT_MCHK. We don't rename it for now, as it will be soon gone (when moving crw machine checks into the flic). Please note that this is the same way also KVM handles it: only one instance of a machine check can be pending at a time. So no need for a queue. While at it, make sure we try to deliver only if env->cregs[14] actually indicates that CRWs are accepted. Drop two unused defines on the way (we already have PSW_MASK_...). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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@ -119,7 +119,6 @@ static void s390_cpu_initial_reset(CPUState *s)
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for (i = 0; i < ARRAY_SIZE(env->io_index); i++) {
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env->io_index[i] = -1;
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}
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env->mchk_index = -1;
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/* tininess for underflow is detected before rounding */
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set_float_detect_tininess(float_tininess_before_rounding,
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@ -156,7 +155,6 @@ static void s390_cpu_full_reset(CPUState *s)
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for (i = 0; i < ARRAY_SIZE(env->io_index); i++) {
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env->io_index[i] = -1;
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}
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env->mchk_index = -1;
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/* tininess for underflow is detected before rounding */
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set_float_detect_tininess(float_tininess_before_rounding,
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@ -54,10 +54,6 @@
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#define MMU_USER_IDX 0
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#define MAX_IO_QUEUE 16
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#define MAX_MCHK_QUEUE 16
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#define PSW_MCHK_MASK 0x0004000000000000
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#define PSW_IO_MASK 0x0200000000000000
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#define S390_MAX_CPUS 248
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@ -73,10 +69,6 @@ typedef struct IOIntQueue {
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uint32_t word;
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} IOIntQueue;
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typedef struct MchkQueue {
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uint16_t type;
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} MchkQueue;
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struct CPUS390XState {
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uint64_t regs[16]; /* GP registers */
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/*
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@ -123,14 +115,12 @@ struct CPUS390XState {
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uint64_t cregs[16]; /* control registers */
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IOIntQueue io_queue[MAX_IO_QUEUE][8];
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MchkQueue mchk_queue[MAX_MCHK_QUEUE];
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int pending_int;
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uint32_t service_param;
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uint16_t external_call_addr;
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DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
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int io_index[8];
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int mchk_index;
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uint64_t ckc;
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uint64_t cputm;
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@ -368,30 +368,16 @@ static void do_io_interrupt(CPUS390XState *env)
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static void do_mchk_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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uint64_t mask, addr;
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LowCore *lowcore;
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MchkQueue *q;
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int i;
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if (!(env->psw.mask & PSW_MASK_MCHECK)) {
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cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
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}
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/* for now we only support channel report machine checks (floating) */
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g_assert(env->psw.mask & PSW_MASK_MCHECK);
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g_assert(env->cregs[14] & CR14_CHANNEL_REPORT_SC);
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if (env->mchk_index < 0 || env->mchk_index >= MAX_MCHK_QUEUE) {
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cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
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}
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q = &env->mchk_queue[env->mchk_index];
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if (q->type != 1) {
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/* Don't know how to handle this... */
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cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
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}
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if (!(env->cregs[14] & (1 << 28))) {
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/* CRW machine checks disabled */
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return;
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}
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g_assert(env->pending_int & INTERRUPT_MCHK);
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env->pending_int &= ~INTERRUPT_MCHK;
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lowcore = cpu_map_lowcore(env);
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@ -418,11 +404,6 @@ static void do_mchk_interrupt(CPUS390XState *env)
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cpu_unmap_lowcore(lowcore);
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env->mchk_index--;
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if (env->mchk_index == -1) {
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env->pending_int &= ~INTERRUPT_MCHK;
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}
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DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
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env->psw.mask, env->psw.addr);
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@ -162,16 +162,6 @@ static void cpu_inject_crw_mchk(S390CPU *cpu)
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{
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CPUS390XState *env = &cpu->env;
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if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
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/* ugh - can't queue anymore. Let's drop. */
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return;
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}
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env->mchk_index++;
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assert(env->mchk_index < MAX_MCHK_QUEUE);
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env->mchk_queue[env->mchk_index].type = 1;
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env->pending_int |= INTERRUPT_MCHK;
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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@ -225,7 +215,13 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu)
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return false;
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}
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return env->pending_int & INTERRUPT_MCHK;
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/* for now we only support channel report machine checks (floating) */
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if ((env->pending_int & INTERRUPT_MCHK) &&
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(env->cregs[14] & CR14_CHANNEL_REPORT_SC)) {
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return true;
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}
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return false;
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}
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bool s390_cpu_has_ext_int(S390CPU *cpu)
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