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* target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()

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* hw/arm: do not free machine->fdt in arm_load_dtb()
  * target/arm: Fix generated code for cpreg reads when HSTR is active
  * hw/ssi: Fix Linux driver init issue with xilinx_spi
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Merge tag 'pull-target-arm-20230403' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

 * target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()
 * hw/arm: do not free machine->fdt in arm_load_dtb()
 * target/arm: Fix generated code for cpreg reads when HSTR is active
 * hw/ssi: Fix Linux driver init issue with xilinx_spi

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# gpg: Signature made Mon 03 Apr 2023 17:00:44 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230403' of https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/ssi: Fix Linux driver init issue with xilinx_spi
  target/arm: Fix generated code for cpreg reads when HSTR is active
  hw/arm: do not free machine->fdt in arm_load_dtb()
  target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-04-03 17:01:47 +01:00
commit 51a6dc9d39
6 changed files with 27 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
hw/arm/boot.c
View File

@ -689,7 +689,10 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
rom_ptr_for_as(as, addr, size));
g_free(fdt);
if (fdt != ms->fdt) {
g_free(ms->fdt);
ms->fdt = fdt;
}
return size;

1
hw/ssi/xilinx_spi.c
View File

@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s)
txfifo_reset(s);
s->regs[R_SPISSR] = ~0;
s->regs[R_SPICR] = R_SPICR_MTI;
xlx_spi_update_irq(s);
xlx_spi_update_cs(s);
}

7
target/arm/gdbstub64.c
View File

@ -230,8 +230,11 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
{
bool is_data = !(reg & 1);
bool is_high = reg & 2;
uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
return gdb_get_reg64(buf, mask);
ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
ARMVAParameters param;
param = aa64_va_parameters(env, -is_high, mmu_idx, is_data);
return gdb_get_reg64(buf, pauth_ptr_mask(param));
}
default:
return 0;

15
target/arm/internals.h
View File

@ -1391,13 +1391,18 @@ bool arm_generate_debug_exceptions(CPUARMState *env);
/**
* pauth_ptr_mask:
* @env: cpu context
* @ptr: selects between TTBR0 and TTBR1
* @data: selects between TBI and TBID
* @param: parameters defining the MMU setup
*
* Return a mask of the bits of @ptr that contain the authentication code.
* Return a mask of the address bits that contain the authentication code,
* given the MMU config defined by @param.
*/
uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
static inline uint64_t pauth_ptr_mask(ARMVAParameters param)
{
int bot_pac_bit = 64 - param.tsz;
int top_pac_bit = 64 - 8 * param.tbi;
return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
}
/* Add the cpreg definitions for debug related system registers */
void define_debug_regs(ARMCPU *cpu);

18
target/arm/tcg/pauth_helper.c
View File

@ -339,17 +339,9 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
return pac | ext | ptr;
}
static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
{
int bot_pac_bit = 64 - param.tsz;
int top_pac_bit = 64 - 8 * param.tbi;
return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
}
static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
{
uint64_t mask = pauth_ptr_mask_internal(param);
uint64_t mask = pauth_ptr_mask(param);
/* Note that bit 55 is used whether or not the regime has 2 ranges. */
if (extract64(ptr, 55, 1)) {
@ -359,14 +351,6 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
}
}
uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
{
ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
return pauth_ptr_mask_internal(param);
}
static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
ARMPACKey *key, bool data, int keynumber)
{

6
target/arm/tcg/translate.c
View File

@ -4623,6 +4623,12 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
/*
* gen_exception_insn() will set is_jmp to DISAS_NORETURN,
* but since we're conditionally branching over it, we want
* to assume continue-to-next-instruction.
*/
s->base.is_jmp = DISAS_NEXT;
set_disas_label(s, over);
}
}