tcg/mips: Split out target constraints to tcg-target-con-str.h
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson
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tcg/mips/tcg-target-con-str.h
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24
tcg/mips/tcg-target-con-str.h
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/* SPDX-License-Identifier: MIT */
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/*
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* Define MIPS target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('L', ALL_QLOAD_REGS)
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REGS('S', ALL_QSTORE_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_U16)
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CONST('J', TCG_CT_CONST_S16)
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CONST('K', TCG_CT_CONST_P2M1)
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CONST('N', TCG_CT_CONST_N16)
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CONST('W', TCG_CT_CONST_WSZ)
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CONST('Z', TCG_CT_CONST_ZERO)
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@ -171,67 +171,27 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
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#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
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#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
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#define TCG_CT_CONST_WSZ 0x2000 /* word size */
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#define TCG_CT_CONST_WSZ 0x2000 /* word size */
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#define ALL_GENERAL_REGS 0xffffffffu
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#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
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#ifdef CONFIG_SOFTMMU
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#define ALL_QLOAD_REGS \
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(NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
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#define ALL_QSTORE_REGS \
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(NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
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? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
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: (1 << TCG_REG_A1)))
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#else
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#define ALL_QLOAD_REGS NOA0_REGS
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#define ALL_QSTORE_REGS NOA0_REGS
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#endif
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static inline bool is_p2m1(tcg_target_long val)
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static inline bool is_p2m1(tcg_target_long val)
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{
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{
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return val && ((val + 1) & val) == 0;
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return val && ((val + 1) & val) == 0;
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}
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}
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/* parse target specific constraints */
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static const char *target_parse_constraint(TCGArgConstraint *ct,
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const char *ct_str, TCGType type)
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{
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switch(*ct_str++) {
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case 'r':
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ct->regs = 0xffffffff;
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break;
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case 'L': /* qemu_ld input arg constraint */
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ct->regs = 0xffffffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
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#if defined(CONFIG_SOFTMMU)
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
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}
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#endif
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break;
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case 'S': /* qemu_st constraint */
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ct->regs = 0xffffffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
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#if defined(CONFIG_SOFTMMU)
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
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tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
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} else {
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tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
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}
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#endif
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break;
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case 'I':
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ct->ct |= TCG_CT_CONST_U16;
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break;
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case 'J':
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ct->ct |= TCG_CT_CONST_S16;
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break;
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case 'K':
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ct->ct |= TCG_CT_CONST_P2M1;
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break;
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case 'N':
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ct->ct |= TCG_CT_CONST_N16;
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break;
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case 'W':
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ct->ct |= TCG_CT_CONST_WSZ;
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break;
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case 'Z':
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/* We are cheating a bit here, using the fact that the register
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ZERO is also the register number 0. Hence there is no need
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to check for const_args in each instruction. */
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ct->ct |= TCG_CT_CONST_ZERO;
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break;
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default:
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return NULL;
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}
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return ct_str;
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}
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/* test if a constant matches the constraint */
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
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static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
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const TCGArgConstraint *arg_ct)
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const TCGArgConstraint *arg_ct)
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@ -1697,6 +1657,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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TCGArg a0, a1, a2;
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TCGArg a0, a1, a2;
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int c2;
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int c2;
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/*
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* Note that many operands use the constraint set "rZ".
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* We make use of the fact that 0 is the ZERO register,
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* and hence such cases need not check for const_args.
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*/
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a0 = args[0];
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a0 = args[0];
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a1 = args[1];
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a1 = args[1];
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a2 = args[2];
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a2 = args[2];
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@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#ifdef CONFIG_SOFTMMU
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#ifdef CONFIG_SOFTMMU
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_NEED_LDST_LABELS
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#endif
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#endif
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#define TCG_TARGET_CON_STR_H
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#endif
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#endif
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