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target/arm: Add stubs for aa32 decodetree

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Add the infrastructure that will become the new decoder.
No instructions adjusted so far.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:29:52 -07:00 committed by Peter Maydell
parent 69be3e1376
commit 51409b9e8c
5 changed files with 114 additions and 1 deletions
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18
target/arm/Makefile.objs
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@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(D
$(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
target/arm/translate-sve.o: target/arm/decode-sve.inc.c
target/arm/translate.o: target/arm/decode-vfp.inc.c
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
target/arm/translate.o: target/arm/decode-a32.inc.c
target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
target/arm/translate.o: target/arm/decode-t32.inc.c
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o

23
target/arm/a32-uncond.decode Normal file
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@ -0,0 +1,23 @@
# A32 unconditional instructions
#
# Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
# All insns that have 0xf in insn[31:28] are decoded here.
# All of those that have a COND field in insn[31:28] are in a32.decode
#

23
target/arm/a32.decode Normal file
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@ -0,0 +1,23 @@
# A32 conditional instructions
#
# Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
# All of the insn that have a COND field in insn[31:28] are here.
# All insns that have 0xf in insn[31:28] are in a32-uncond.decode.
#

20
target/arm/t32.decode Normal file
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@ -0,0 +1,20 @@
# Thumb2 instructions
#
# Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#

31
target/arm/translate.c
View File

@ -7683,6 +7683,18 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
arm_gen_test_cc(cond ^ 1, s->condlabel);
}
/*
* Include the generated decoders.
*/
#include "decode-a32.inc.c"
#include "decode-a32-uncond.inc.c"
#include "decode-t32.inc.c"
/*
* Legacy decoder.
*/
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
@ -7701,7 +7713,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
return;
}
cond = insn >> 28;
if (cond == 0xf){
if (cond == 0xf) {
/* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
* choose to UNDEF. In ARMv5 and above the space is used
* for miscellaneous unconditional instructions.
@ -7709,6 +7722,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
ARCH(5);
/* Unconditional instructions. */
if (disas_a32_uncond(s, insn)) {
return;
}
/* fall back to legacy decoder */
if (((insn >> 25) & 7) == 1) {
/* NEON Data processing. */
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@ -7923,6 +7941,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
next instruction */
arm_skip_unless(s, cond);
}
if (disas_a32(s, insn)) {
return;
}
/* fall back to legacy decoder */
if ((insn & 0x0f900000) == 0x03000000) {
if ((insn & (1 << 21)) == 0) {
ARCH(6T2);
@ -9414,6 +9438,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
ARCH(6T2);
}
if (disas_t32(s, insn)) {
return;
}
/* fall back to legacy decoder */
rn = (insn >> 16) & 0xf;
rs = (insn >> 12) & 0xf;
rd = (insn >> 8) & 0xf;