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target/i386: add guest-phys-bits cpu property

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Allows to set guest-phys-bits (cpuid leaf 80000008, eax[23:16])
via -cpu $model,guest-phys-bits=$nr.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-ID: <20240318155336.156197-3-kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Gerd Hoffmann 2024-03-18 16:53:36 +01:00 committed by Paolo Bonzini
parent 85fa9acda8
commit 513ba32dcc
3 changed files with 33 additions and 1 deletions
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4
hw/i386/pc.c
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@ -78,7 +78,9 @@
{ "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
{ "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
GlobalProperty pc_compat_9_0[] = {};
GlobalProperty pc_compat_9_0[] = {
{ TYPE_X86_CPU, "guest-phys-bits", "0" },
};
const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0);
GlobalProperty pc_compat_8_2[] = {};

22
target/i386/cpu.c
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@ -6570,6 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
/* 64 bit processor */
*eax |= (cpu_x86_virtual_addr_width(env) << 8);
*eax |= (cpu->guest_phys_bits << 16);
}
*ebx = env->features[FEAT_8000_0008_EBX];
if (cs->nr_cores * cs->nr_threads > 1) {
@ -7329,6 +7330,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
goto out;
}
if (cpu->guest_phys_bits == -1) {
/*
* If it was not set by the user, or by the accelerator via
* cpu_exec_realizefn, clear.
*/
cpu->guest_phys_bits = 0;
}
if (cpu->ucode_rev == 0) {
/*
* The default is the same as KVM's. Note that this check
@ -7379,6 +7388,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
if (cpu->phys_bits == 0) {
cpu->phys_bits = TCG_PHYS_ADDR_BITS;
}
if (cpu->guest_phys_bits &&
(cpu->guest_phys_bits > cpu->phys_bits ||
cpu->guest_phys_bits < 32)) {
error_setg(errp, "guest-phys-bits should be between 32 and %u "
" (but is %u)",
cpu->phys_bits, cpu->guest_phys_bits);
return;
}
} else {
/* For 32 bit systems don't use the user set value, but keep
* phys_bits consistent with what we tell the guest.
@ -7387,6 +7404,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
error_setg(errp, "phys-bits is not user-configurable in 32 bit");
return;
}
if (cpu->guest_phys_bits != 0) {
error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit");
return;
}
if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) {
cpu->phys_bits = 36;
@ -7887,6 +7908,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1),
DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),

8
target/i386/cpu.h
View File

@ -2027,6 +2027,14 @@ struct ArchCPU {
/* Number of physical address bits supported */
uint32_t phys_bits;
/*
* Number of guest physical address bits available. Usually this is
* identical to host physical address bits. With NPT or EPT 4-level
* paging, guest physical address space might be restricted to 48 bits
* even if the host cpu supports more physical address bits.
*/
uint32_t guest_phys_bits;
/* in order to simplify APIC support, we leave this pointer to the
user */
struct DeviceState *apic_state;