From 51141cab3ba2e1e317667a2a32f3a42ca28c2819 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 22 May 2023 10:31:40 +0200 Subject: [PATCH] hw/char/pl011: Display register name in trace events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To avoid knowing the register addresses by heart, display their name along in the trace events. Since the MMIO region is 4K wide (0x1000 bytes), displaying the address with 3 digits is enough, so reduce the address format. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230522153144.30610-5-philmd@linaro.org> --- hw/char/pl011.c | 25 ++++++++++++++++++++++--- hw/char/trace-events | 4 ++-- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 73f1a3aea2..c3203e5b41 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -51,6 +51,7 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define PL011_INT_TX 0x20 #define PL011_INT_RX 0x10 +/* Flag Register, UARTFR */ #define PL011_FLAG_TXFE 0x80 #define PL011_FLAG_RXFF 0x40 #define PL011_FLAG_TXFF 0x20 @@ -76,6 +77,24 @@ static const unsigned char pl011_id_arm[8] = static const unsigned char pl011_id_luminary[8] = { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; +static const char *pl011_regname(hwaddr offset) +{ + static const char *const rname[] = { + [0] = "DR", [1] = "RSR", [6] = "FR", [8] = "ILPR", [9] = "IBRD", + [10] = "FBRD", [11] = "LCRH", [12] = "CR", [13] = "IFLS", [14] = "IMSC", + [15] = "RIS", [16] = "MIS", [17] = "ICR", [18] = "DMACR", + }; + unsigned idx = offset >> 2; + + if (idx < ARRAY_SIZE(rname) && rname[idx]) { + return rname[idx]; + } + if (idx >= 0x3f8 && idx <= 0x400) { + return "ID"; + } + return "UNKN"; +} + /* Which bits in the interrupt status matter for each outbound IRQ line ? */ static const uint32_t irqmask[] = { INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ @@ -191,7 +210,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, break; } - trace_pl011_read(offset, r); + trace_pl011_read(offset, r, pl011_regname(offset)); return r; } @@ -234,7 +253,7 @@ static void pl011_write(void *opaque, hwaddr offset, PL011State *s = (PL011State *)opaque; unsigned char ch; - trace_pl011_write(offset, value); + trace_pl011_write(offset, value, pl011_regname(offset)); switch (offset >> 2) { case 0: /* UARTDR */ @@ -252,7 +271,7 @@ static void pl011_write(void *opaque, hwaddr offset, case 6: /* UARTFR */ /* Writes to Flag register are ignored. */ break; - case 8: /* UARTUARTILPR */ + case 8: /* UARTILPR */ s->ilpr = value; break; case 9: /* UARTIBRD */ diff --git a/hw/char/trace-events b/hw/char/trace-events index 2ecb36232e..babf4d35ea 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -54,9 +54,9 @@ escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=0x%0 # pl011.c pl011_irq_state(int level) "irq state %d" -pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_read_fifo(int read_count) "FIFO read, read_count now %d" -pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d" pl011_put_fifo_full(void) "FIFO now full, RXFF set"