specialize the power save code for 7x0 CPUs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1671 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -265,11 +265,11 @@ int cpu_exec(CPUState *env1)
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}
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}
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#elif defined(TARGET_PPC)
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if (env1->msr[MSR_POW]) {
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if (env1->halted) {
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if (env1->msr[MSR_EE] &&
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(env1->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
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env1->msr[MSR_POW] = 0;
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env1->halted = 0;
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} else {
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return EXCP_HALTED;
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}
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@ -257,7 +257,7 @@ static void do_info_cpus(void)
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term_printf(" (halted)");
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#elif defined(TARGET_PPC)
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term_printf(" nip=0x" TARGET_FMT_lx, env->nip);
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if (msr_pow)
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if (env->halted)
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term_printf(" (halted)");
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#endif
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term_printf("\n");
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@ -495,6 +495,8 @@ struct CPUPPCState {
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CPU_COMMON
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int halted; /* TRUE if the CPU is in suspend state */
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int access_type; /* when a memory exception occurs, the access
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type is stored here */
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@ -807,6 +807,8 @@ void do_compute_hflags (CPUPPCState *env)
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void do_store_msr (CPUPPCState *env, target_ulong value)
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{
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int enter_pm;
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value &= env->msr_mask;
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if (((value >> MSR_IR) & 1) != msr_ir ||
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((value >> MSR_DR) & 1) != msr_dr) {
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@ -846,8 +848,19 @@ void do_store_msr (CPUPPCState *env, target_ulong value)
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msr_ri = (value >> MSR_RI) & 1;
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msr_le = (value >> MSR_LE) & 1;
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do_compute_hflags(env);
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if (msr_pow) {
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enter_pm = 0;
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switch (PPC_EXCP(env)) {
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case PPC_FLAGS_EXCP_7x0:
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if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
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enter_pm = 1;
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break;
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default:
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break;
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}
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if (enter_pm) {
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/* power save: exit cpu loop */
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env->halted = 1;
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env->exception_index = EXCP_HLT;
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cpu_loop_exit();
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}
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