RISC-V HTIF Console
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com>
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Michael Clark
parent
a2480ffa88
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258
hw/riscv/riscv_htif.c
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258
hw/riscv/riscv_htif.c
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/*
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* QEMU RISC-V Host Target Interface (HTIF) Emulation
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This provides HTIF device emulation for QEMU. At the moment this allows
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* for identical copies of bbl/linux to run on both spike and QEMU.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "chardev/char.h"
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#include "chardev/char-fe.h"
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#include "hw/riscv/riscv_htif.h"
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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#include "qemu/error-report.h"
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#define RISCV_DEBUG_HTIF 0
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#define HTIF_DEBUG(fmt, ...) \
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do { \
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if (RISCV_DEBUG_HTIF) { \
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qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
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} \
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} while (0)
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static uint64_t fromhost_addr, tohost_addr;
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void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
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uint64_t st_size)
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{
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if (strcmp("fromhost", st_name) == 0) {
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fromhost_addr = st_value;
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if (st_size != 8) {
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error_report("HTIF fromhost must be 8 bytes");
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exit(1);
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}
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} else if (strcmp("tohost", st_name) == 0) {
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tohost_addr = st_value;
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if (st_size != 8) {
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error_report("HTIF tohost must be 8 bytes");
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exit(1);
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}
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}
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}
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/*
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* Called by the char dev to see if HTIF is ready to accept input.
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*/
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static int htif_can_recv(void *opaque)
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{
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return 1;
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}
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/*
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* Called by the char dev to supply input to HTIF console.
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* We assume that we will receive one character at a time.
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*/
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static void htif_recv(void *opaque, const uint8_t *buf, int size)
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{
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HTIFState *htifstate = opaque;
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if (size != 1) {
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return;
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}
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/* TODO - we need to check whether mfromhost is zero which indicates
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the device is ready to receive. The current implementation
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will drop characters */
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uint64_t val_written = htifstate->pending_read;
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uint64_t resp = 0x100 | *buf;
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htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
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}
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/*
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* Called by the char dev to supply special events to the HTIF console.
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* Not used for HTIF.
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*/
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static void htif_event(void *opaque, int event)
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{
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}
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static int htif_be_change(void *opaque)
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{
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HTIFState *s = opaque;
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qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
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htif_be_change, s, NULL, true);
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return 0;
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}
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static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
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{
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uint8_t device = val_written >> 56;
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uint8_t cmd = val_written >> 48;
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uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
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int resp = 0;
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HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64
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" -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload);
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/*
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* Currently, there is a fixed mapping of devices:
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* 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
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* 1: Console
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*/
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if (unlikely(device == 0x0)) {
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/* frontend syscall handler, shutdown and exit code support */
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if (cmd == 0x0) {
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if (payload & 0x1) {
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/* exit code */
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int exit_code = payload >> 1;
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exit(exit_code);
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} else {
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qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n");
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}
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} else {
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qemu_log("HTIF device %d: unknown command\n", device);
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}
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} else if (likely(device == 0x1)) {
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/* HTIF Console */
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if (cmd == 0x0) {
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/* this should be a queue, but not yet implemented as such */
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htifstate->pending_read = val_written;
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htifstate->env->mtohost = 0; /* clear to indicate we read */
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return;
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} else if (cmd == 0x1) {
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qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
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resp = 0x100 | (uint8_t)payload;
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} else {
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qemu_log("HTIF device %d: unknown command\n", device);
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}
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} else {
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qemu_log("HTIF unknown device or command\n");
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HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64
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" payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
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}
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/*
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* - latest bbl does not set fromhost to 0 if there is a value in tohost
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* - with this code enabled, qemu hangs waiting for fromhost to go to 0
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* - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10
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* - HTIF needs protocol documentation and a more complete state machine
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while (!htifstate->fromhost_inprogress &&
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htifstate->env->mfromhost != 0x0) {
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}
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*/
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htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
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htifstate->env->mtohost = 0; /* clear to indicate we read */
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}
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#define TOHOST_OFFSET1 (htifstate->tohost_offset)
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#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4)
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#define FROMHOST_OFFSET1 (htifstate->fromhost_offset)
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#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4)
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/* CPU wants to read an HTIF register */
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static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
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{
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HTIFState *htifstate = opaque;
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if (addr == TOHOST_OFFSET1) {
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return htifstate->env->mtohost & 0xFFFFFFFF;
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} else if (addr == TOHOST_OFFSET2) {
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return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF;
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} else if (addr == FROMHOST_OFFSET1) {
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return htifstate->env->mfromhost & 0xFFFFFFFF;
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} else if (addr == FROMHOST_OFFSET2) {
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return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF;
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} else {
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qemu_log("Invalid htif read: address %016" PRIx64 "\n",
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(uint64_t)addr);
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return 0;
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}
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}
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/* CPU wrote to an HTIF register */
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static void htif_mm_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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HTIFState *htifstate = opaque;
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if (addr == TOHOST_OFFSET1) {
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if (htifstate->env->mtohost == 0x0) {
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htifstate->allow_tohost = 1;
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htifstate->env->mtohost = value & 0xFFFFFFFF;
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} else {
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htifstate->allow_tohost = 0;
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}
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} else if (addr == TOHOST_OFFSET2) {
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if (htifstate->allow_tohost) {
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htifstate->env->mtohost |= value << 32;
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htif_handle_tohost_write(htifstate, htifstate->env->mtohost);
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}
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} else if (addr == FROMHOST_OFFSET1) {
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htifstate->fromhost_inprogress = 1;
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htifstate->env->mfromhost = value & 0xFFFFFFFF;
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} else if (addr == FROMHOST_OFFSET2) {
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htifstate->env->mfromhost |= value << 32;
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htifstate->fromhost_inprogress = 0;
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} else {
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qemu_log("Invalid htif write: address %016" PRIx64 "\n",
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(uint64_t)addr);
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}
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}
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static const MemoryRegionOps htif_mm_ops = {
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.read = htif_mm_read,
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.write = htif_mm_write,
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};
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HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
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CPURISCVState *env, Chardev *chr)
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{
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uint64_t base = MIN(tohost_addr, fromhost_addr);
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uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
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uint64_t tohost_offset = tohost_addr - base;
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uint64_t fromhost_offset = fromhost_addr - base;
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HTIFState *s = g_malloc0(sizeof(HTIFState));
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s->address_space = address_space;
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s->main_mem = main_mem;
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s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem);
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s->env = env;
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s->tohost_offset = tohost_offset;
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s->fromhost_offset = fromhost_offset;
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s->pending_read = 0;
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s->allow_tohost = 0;
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s->fromhost_inprogress = 0;
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qemu_chr_fe_init(&s->chr, chr, &error_abort);
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qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
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htif_be_change, s, NULL, true);
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if (base) {
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memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
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TYPE_HTIF_UART, size);
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memory_region_add_subregion(address_space, base, &s->mmio);
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}
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return s;
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}
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61
include/hw/riscv/riscv_htif.h
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61
include/hw/riscv/riscv_htif.h
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/*
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* QEMU RISCV Host Target Interface (HTIF) Emulation
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_HTIF_H
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#define HW_RISCV_HTIF_H
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#include "hw/hw.h"
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#include "chardev/char.h"
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#include "chardev/char-fe.h"
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#include "sysemu/sysemu.h"
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#include "exec/memory.h"
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#include "target/riscv/cpu.h"
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#define TYPE_HTIF_UART "riscv.htif.uart"
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typedef struct HTIFState {
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int allow_tohost;
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int fromhost_inprogress;
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hwaddr tohost_offset;
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hwaddr fromhost_offset;
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uint64_t tohost_size;
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uint64_t fromhost_size;
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MemoryRegion mmio;
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MemoryRegion *address_space;
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MemoryRegion *main_mem;
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void *main_mem_ram_ptr;
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CPURISCVState *env;
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CharBackend chr;
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uint64_t pending_read;
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} HTIFState;
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extern const VMStateDescription vmstate_htif;
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extern const MemoryRegionOps htif_io_ops;
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/* HTIF symbol callback */
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void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
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uint64_t st_size);
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/* legacy pre qom */
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HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
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CPURISCVState *env, Chardev *chr);
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#endif
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