usb/ehci: seperate out PCIisms
Seperate the PCI stuff from the EHCI components. Extracted the PCIDevice out into a new wrapper struct to make EHCIState non-PCI-specific. Seperated tho non PCI init component out into a seperate "common" init function. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Peter Crosthwaite
Gerd Hoffmann
parent
7ae6ce0258
commit
5010d4dc61
@ -385,7 +385,6 @@ struct EHCIQueue {
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typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
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struct EHCIState {
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PCIDevice dev;
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USBBus bus;
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qemu_irq irq;
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MemoryRegion mem;
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@ -447,6 +446,11 @@ struct EHCIState {
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bool int_req_by_async;
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};
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typedef struct EHCIPCIState {
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PCIDevice pcidev;
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EHCIState ehci;
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} EHCIPCIState;
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#define SET_LAST_RUN_CLOCK(s) \
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(s)->last_run_ns = qemu_get_clock_ns(vm_clock);
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@ -2553,7 +2557,7 @@ static const MemoryRegionOps ehci_mmio_port_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int usb_ehci_initfn(PCIDevice *dev);
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static int usb_ehci_pci_initfn(PCIDevice *dev);
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static USBPortOps ehci_port_ops = {
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.attach = ehci_attach,
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@ -2614,12 +2618,11 @@ static void usb_ehci_vm_state_change(void *opaque, int running, RunState state)
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}
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static const VMStateDescription vmstate_ehci = {
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.name = "ehci",
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.name = "ehci-core",
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.version_id = 2,
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.minimum_version_id = 1,
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.post_load = usb_ehci_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, EHCIState),
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/* mmio registers */
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VMSTATE_UINT32(usbcmd, EHCIState),
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VMSTATE_UINT32(usbsts, EHCIState),
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@ -2650,8 +2653,19 @@ static const VMStateDescription vmstate_ehci = {
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}
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};
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static Property ehci_properties[] = {
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DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
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static const VMStateDescription vmstate_ehci_pci = {
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.name = "ehci",
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.version_id = 2,
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.minimum_version_id = 1,
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.post_load = usb_ehci_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState),
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VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState),
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}
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};
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static Property ehci_pci_properties[] = {
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DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -2660,13 +2674,13 @@ static void ehci_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = usb_ehci_initfn;
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k->init = usb_ehci_pci_initfn;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
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k->revision = 0x10;
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k->class_id = PCI_CLASS_SERIAL_USB;
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dc->vmsd = &vmstate_ehci;
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dc->props = ehci_properties;
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dc->props = ehci_pci_properties;
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}
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static TypeInfo ehci_info = {
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@ -2681,13 +2695,13 @@ static void ich9_ehci_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = usb_ehci_initfn;
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k->init = usb_ehci_pci_initfn;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
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k->revision = 0x03;
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k->class_id = PCI_CLASS_SERIAL_USB;
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dc->vmsd = &vmstate_ehci;
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dc->props = ehci_properties;
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dc->props = ehci_pci_properties;
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}
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static TypeInfo ich9_ehci_info = {
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@ -2697,44 +2711,10 @@ static TypeInfo ich9_ehci_info = {
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.class_init = ich9_ehci_class_init,
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};
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static int usb_ehci_initfn(PCIDevice *dev)
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static void usb_ehci_initfn(EHCIState *s, DeviceState *dev)
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{
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EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
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uint8_t *pci_conf = s->dev.config;
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int i;
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pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
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/* capabilities pointer */
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pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
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//pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
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pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
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pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
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pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
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// pci_conf[0x50] = 0x01; // power management caps
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pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
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pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
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pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
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pci_conf[0x64] = 0x00;
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pci_conf[0x65] = 0x00;
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pci_conf[0x66] = 0x00;
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pci_conf[0x67] = 0x00;
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pci_conf[0x68] = 0x01;
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pci_conf[0x69] = 0x00;
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pci_conf[0x6a] = 0x00;
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pci_conf[0x6b] = 0x00; // USBLEGSUP
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pci_conf[0x6c] = 0x00;
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pci_conf[0x6d] = 0x00;
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pci_conf[0x6e] = 0x00;
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pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
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s->capsbase = 0x00;
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s->opregbase = 0x20;
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/* 2.2 host controller interface version */
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s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
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s->caps[0x01] = 0x00;
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@ -2745,15 +2725,10 @@ static int usb_ehci_initfn(PCIDevice *dev)
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s->caps[0x06] = 0x00;
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s->caps[0x07] = 0x00;
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s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
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s->caps[0x09] = 0x68; /* EECP */
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s->caps[0x0a] = 0x00;
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s->caps[0x0b] = 0x00;
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s->irq = s->dev.irq[3];
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s->dma = pci_dma_context(dev);
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usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
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usb_bus_new(&s->bus, &ehci_bus_ops, dev);
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for(i = 0; i < NB_PORTS; i++) {
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usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
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USB_SPEED_MASK_HIGH);
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@ -2781,8 +2756,53 @@ static int usb_ehci_initfn(PCIDevice *dev)
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memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg);
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memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN,
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&s->mem_ports);
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}
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pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
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static int usb_ehci_pci_initfn(PCIDevice *dev)
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{
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EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev);
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EHCIState *s = &i->ehci;
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uint8_t *pci_conf = dev->config;
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pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
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/* capabilities pointer */
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pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
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/* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */
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pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
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pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
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pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
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/* pci_conf[0x50] = 0x01; *//* power management caps */
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pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.1.4) */
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pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (2.1.5) */
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pci_set_word(&pci_conf[0x62], 0x00); /* port wake up capability (2.1.6) */
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pci_conf[0x64] = 0x00;
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pci_conf[0x65] = 0x00;
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pci_conf[0x66] = 0x00;
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pci_conf[0x67] = 0x00;
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pci_conf[0x68] = 0x01;
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pci_conf[0x69] = 0x00;
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pci_conf[0x6a] = 0x00;
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pci_conf[0x6b] = 0x00; /* USBLEGSUP */
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pci_conf[0x6c] = 0x00;
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pci_conf[0x6d] = 0x00;
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pci_conf[0x6e] = 0x00;
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pci_conf[0x6f] = 0xc0; /* USBLEFCTLSTS */
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s->caps[0x09] = 0x68; /* EECP */
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s->irq = dev->irq[3];
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s->dma = pci_dma_context(dev);
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s->capsbase = 0x00;
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s->opregbase = 0x20;
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usb_ehci_initfn(s, DEVICE(dev));
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pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
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return 0;
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}
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