exec: introduce tlb_init
Paves the way for the addition of a per-TLB lock. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20181009174557.16125-4-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -73,6 +73,10 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
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QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
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#define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
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void tlb_init(CPUState *cpu)
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{
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}
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/* flush_all_helper: run fn across all cpus
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*
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* If the wait flag is set then the src cpu's helper will be queued as
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1
exec.c
1
exec.c
@ -965,6 +965,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
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tcg_target_initialized = true;
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cc->tcg_initialize();
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}
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tlb_init(cpu);
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#ifndef CONFIG_USER_ONLY
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if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
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@ -99,6 +99,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx,
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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/* cputlb.c */
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/**
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* tlb_init - initialize a CPU's TLB
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* @cpu: CPU whose TLB should be initialized
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*/
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void tlb_init(CPUState *cpu);
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/**
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* tlb_flush_page:
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* @cpu: CPU whose TLB should be flushed
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@ -258,6 +263,9 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
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void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
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uintptr_t retaddr);
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#else
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static inline void tlb_init(CPUState *cpu)
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{
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}
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static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
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{
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}
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