hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module
The Arm Cortex-M System Design Kit includes a "dual-input timer module" which combines two programmable down-counters. Implement a model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-4-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
93739075d2
commit
4f4c6206ca
@ -455,6 +455,8 @@ F: hw/timer/pl031.c
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F: include/hw/arm/primecell.h
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F: include/hw/arm/primecell.h
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F: hw/timer/cmsdk-apb-timer.c
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F: hw/timer/cmsdk-apb-timer.c
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F: include/hw/timer/cmsdk-apb-timer.h
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F: include/hw/timer/cmsdk-apb-timer.h
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F: hw/timer/cmsdk-apb-dualtimer.c
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F: include/hw/timer/cmsdk-apb-dualtimer.h
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F: hw/char/cmsdk-apb-uart.c
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F: hw/char/cmsdk-apb-uart.c
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F: include/hw/char/cmsdk-apb-uart.h
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F: include/hw/char/cmsdk-apb-uart.h
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F: hw/watchdog/cmsdk-apb-watchdog.c
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F: hw/watchdog/cmsdk-apb-watchdog.c
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@ -103,6 +103,7 @@ CONFIG_STM32F2XX_SPI=y
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CONFIG_STM32F205_SOC=y
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CONFIG_STM32F205_SOC=y
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CONFIG_CMSDK_APB_TIMER=y
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CONFIG_CMSDK_APB_TIMER=y
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CONFIG_CMSDK_APB_DUALTIMER=y
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CONFIG_CMSDK_APB_UART=y
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CONFIG_CMSDK_APB_UART=y
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CONFIG_CMSDK_APB_WATCHDOG=y
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CONFIG_CMSDK_APB_WATCHDOG=y
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@ -44,4 +44,5 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
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common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
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common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
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common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
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common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
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common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) += cmsdk-apb-dualtimer.o
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common-obj-$(CONFIG_MSF2) += mss-timer.o
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common-obj-$(CONFIG_MSF2) += mss-timer.o
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515
hw/timer/cmsdk-apb-dualtimer.c
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515
hw/timer/cmsdk-apb-dualtimer.c
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@ -0,0 +1,515 @@
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/*
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* ARM CMSDK APB dual-timer emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "APB dual-input timer" which is part of the Cortex-M
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* System Design Kit (CMSDK) and documented in the Cortex-M System
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* Design Kit Technical Reference Manual (ARM DDI0479C):
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* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "qemu/main-loop.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/timer/cmsdk-apb-dualtimer.h"
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REG32(TIMER1LOAD, 0x0)
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REG32(TIMER1VALUE, 0x4)
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REG32(TIMER1CONTROL, 0x8)
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FIELD(CONTROL, ONESHOT, 0, 1)
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FIELD(CONTROL, SIZE, 1, 1)
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FIELD(CONTROL, PRESCALE, 2, 2)
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FIELD(CONTROL, INTEN, 5, 1)
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FIELD(CONTROL, MODE, 6, 1)
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FIELD(CONTROL, ENABLE, 7, 1)
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#define R_CONTROL_VALID_MASK (R_CONTROL_ONESHOT_MASK | R_CONTROL_SIZE_MASK | \
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R_CONTROL_PRESCALE_MASK | R_CONTROL_INTEN_MASK | \
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R_CONTROL_MODE_MASK | R_CONTROL_ENABLE_MASK)
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REG32(TIMER1INTCLR, 0xc)
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REG32(TIMER1RIS, 0x10)
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REG32(TIMER1MIS, 0x14)
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REG32(TIMER1BGLOAD, 0x18)
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REG32(TIMER2LOAD, 0x20)
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REG32(TIMER2VALUE, 0x24)
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REG32(TIMER2CONTROL, 0x28)
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REG32(TIMER2INTCLR, 0x2c)
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REG32(TIMER2RIS, 0x30)
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REG32(TIMER2MIS, 0x34)
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REG32(TIMER2BGLOAD, 0x38)
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REG32(TIMERITCR, 0xf00)
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FIELD(TIMERITCR, ENABLE, 0, 1)
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#define R_TIMERITCR_VALID_MASK R_TIMERITCR_ENABLE_MASK
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REG32(TIMERITOP, 0xf04)
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FIELD(TIMERITOP, TIMINT1, 0, 1)
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FIELD(TIMERITOP, TIMINT2, 1, 1)
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#define R_TIMERITOP_VALID_MASK (R_TIMERITOP_TIMINT1_MASK | \
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R_TIMERITOP_TIMINT2_MASK)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* PID/CID values */
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static const int timer_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x23, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static bool cmsdk_dualtimermod_intstatus(CMSDKAPBDualTimerModule *m)
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{
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/* Return masked interrupt status for the timer module */
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return m->intstatus && (m->control & R_CONTROL_INTEN_MASK);
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}
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static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s)
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{
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bool timint1, timint2, timintc;
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if (s->timeritcr) {
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/* Integration test mode: outputs driven directly from TIMERITOP bits */
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timint1 = s->timeritop & R_TIMERITOP_TIMINT1_MASK;
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timint2 = s->timeritop & R_TIMERITOP_TIMINT2_MASK;
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} else {
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timint1 = cmsdk_dualtimermod_intstatus(&s->timermod[0]);
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timint2 = cmsdk_dualtimermod_intstatus(&s->timermod[1]);
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}
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timintc = timint1 || timint2;
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qemu_set_irq(s->timermod[0].timerint, timint1);
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qemu_set_irq(s->timermod[1].timerint, timint2);
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qemu_set_irq(s->timerintc, timintc);
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}
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static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
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uint32_t newctrl)
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{
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/* Handle a write to the CONTROL register */
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uint32_t changed;
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newctrl &= R_CONTROL_VALID_MASK;
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changed = m->control ^ newctrl;
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if (changed & ~newctrl & R_CONTROL_ENABLE_MASK) {
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/* ENABLE cleared, stop timer before any further changes */
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ptimer_stop(m->timer);
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}
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if (changed & R_CONTROL_PRESCALE_MASK) {
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int divisor;
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switch (FIELD_EX32(newctrl, CONTROL, PRESCALE)) {
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case 0:
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divisor = 1;
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break;
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case 1:
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divisor = 16;
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break;
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case 2:
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divisor = 256;
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break;
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case 3:
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/* UNDEFINED; complain, and arbitrarily treat like 2 */
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB dual-timer: CONTROL.PRESCALE==0b11"
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" is undefined behaviour\n");
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divisor = 256;
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break;
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default:
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g_assert_not_reached();
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}
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ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor);
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}
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if (changed & R_CONTROL_MODE_MASK) {
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uint32_t load;
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if (newctrl & R_CONTROL_MODE_MASK) {
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/* Periodic: the limit is the LOAD register value */
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load = m->load;
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} else {
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/* Free-running: counter wraps around */
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load = ptimer_get_limit(m->timer);
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if (!(m->control & R_CONTROL_SIZE_MASK)) {
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load = deposit32(m->load, 0, 16, load);
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}
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m->load = load;
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load = 0xffffffff;
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}
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if (!(m->control & R_CONTROL_SIZE_MASK)) {
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load &= 0xffff;
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}
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ptimer_set_limit(m->timer, load, 0);
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}
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if (changed & R_CONTROL_SIZE_MASK) {
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/* Timer switched between 16 and 32 bit count */
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uint32_t value, load;
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value = ptimer_get_count(m->timer);
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load = ptimer_get_limit(m->timer);
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if (newctrl & R_CONTROL_SIZE_MASK) {
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/* 16 -> 32, top half of VALUE is in struct field */
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value = deposit32(m->value, 0, 16, value);
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} else {
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/* 32 -> 16: save top half to struct field and truncate */
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m->value = value;
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value &= 0xffff;
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}
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if (newctrl & R_CONTROL_MODE_MASK) {
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/* Periodic, timer limit has LOAD value */
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if (newctrl & R_CONTROL_SIZE_MASK) {
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load = deposit32(m->load, 0, 16, load);
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} else {
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m->load = load;
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load &= 0xffff;
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}
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} else {
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/* Free-running, timer limit is set to give wraparound */
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if (newctrl & R_CONTROL_SIZE_MASK) {
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load = 0xffffffff;
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} else {
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load = 0xffff;
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}
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}
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ptimer_set_count(m->timer, value);
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ptimer_set_limit(m->timer, load, 0);
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}
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if (newctrl & R_CONTROL_ENABLE_MASK) {
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/*
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* ENABLE is set; start the timer after all other changes.
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* We start it even if the ENABLE bit didn't actually change,
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* in case the timer was an expired one-shot timer that has
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* now been changed into a free-running or periodic timer.
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*/
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ptimer_run(m->timer, !!(newctrl & R_CONTROL_ONESHOT_MASK));
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}
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m->control = newctrl;
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}
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static uint64_t cmsdk_apb_dualtimer_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque);
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uint64_t r;
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if (offset >= A_TIMERITCR) {
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switch (offset) {
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case A_TIMERITCR:
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r = s->timeritcr;
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break;
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case A_PID4 ... A_CID3:
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r = timer_id[(offset - A_PID4) / 4];
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break;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB dual-timer read: bad offset %x\n",
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(int) offset);
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r = 0;
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break;
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}
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} else {
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int timer = offset >> 5;
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CMSDKAPBDualTimerModule *m;
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if (timer >= ARRAY_SIZE(s->timermod)) {
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goto bad_offset;
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}
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m = &s->timermod[timer];
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switch (offset & 0x1F) {
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case A_TIMER1LOAD:
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case A_TIMER1BGLOAD:
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if (m->control & R_CONTROL_MODE_MASK) {
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/*
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* Periodic: the ptimer limit is the LOAD register value, (or
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* just the low 16 bits of it if the timer is in 16-bit mode)
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*/
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r = ptimer_get_limit(m->timer);
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if (!(m->control & R_CONTROL_SIZE_MASK)) {
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r = deposit32(m->load, 0, 16, r);
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}
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} else {
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/* Free-running: LOAD register value is just in m->load */
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r = m->load;
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}
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break;
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case A_TIMER1VALUE:
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r = ptimer_get_count(m->timer);
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if (!(m->control & R_CONTROL_SIZE_MASK)) {
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r = deposit32(m->value, 0, 16, r);
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}
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break;
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case A_TIMER1CONTROL:
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r = m->control;
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break;
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case A_TIMER1RIS:
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r = m->intstatus;
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break;
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case A_TIMER1MIS:
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r = cmsdk_dualtimermod_intstatus(m);
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break;
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default:
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goto bad_offset;
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}
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}
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trace_cmsdk_apb_dualtimer_read(offset, r, size);
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return r;
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}
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static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque);
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trace_cmsdk_apb_dualtimer_write(offset, value, size);
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if (offset >= A_TIMERITCR) {
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switch (offset) {
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case A_TIMERITCR:
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s->timeritcr = value & R_TIMERITCR_VALID_MASK;
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cmsdk_apb_dualtimer_update(s);
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case A_TIMERITOP:
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s->timeritop = value & R_TIMERITOP_VALID_MASK;
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cmsdk_apb_dualtimer_update(s);
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB dual-timer write: bad offset %x\n",
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(int) offset);
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break;
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}
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} else {
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int timer = offset >> 5;
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CMSDKAPBDualTimerModule *m;
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if (timer >= ARRAY_SIZE(s->timermod)) {
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goto bad_offset;
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}
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m = &s->timermod[timer];
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switch (offset & 0x1F) {
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case A_TIMER1LOAD:
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/* Set the limit, and immediately reload the count from it */
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m->load = value;
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m->value = value;
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if (!(m->control & R_CONTROL_SIZE_MASK)) {
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|
value &= 0xffff;
|
||||||
|
}
|
||||||
|
if (!(m->control & R_CONTROL_MODE_MASK)) {
|
||||||
|
/*
|
||||||
|
* In free-running mode this won't set the limit but will
|
||||||
|
* still change the current count value.
|
||||||
|
*/
|
||||||
|
ptimer_set_count(m->timer, value);
|
||||||
|
} else {
|
||||||
|
if (!value) {
|
||||||
|
ptimer_stop(m->timer);
|
||||||
|
}
|
||||||
|
ptimer_set_limit(m->timer, value, 1);
|
||||||
|
if (value && (m->control & R_CONTROL_ENABLE_MASK)) {
|
||||||
|
/* Force possibly-expired oneshot timer to restart */
|
||||||
|
ptimer_run(m->timer, 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case A_TIMER1BGLOAD:
|
||||||
|
/* Set the limit, but not the current count */
|
||||||
|
m->load = value;
|
||||||
|
if (!(m->control & R_CONTROL_MODE_MASK)) {
|
||||||
|
/* In free-running mode there is no limit */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (!(m->control & R_CONTROL_SIZE_MASK)) {
|
||||||
|
value &= 0xffff;
|
||||||
|
}
|
||||||
|
ptimer_set_limit(m->timer, value, 0);
|
||||||
|
break;
|
||||||
|
case A_TIMER1CONTROL:
|
||||||
|
cmsdk_dualtimermod_write_control(m, value);
|
||||||
|
cmsdk_apb_dualtimer_update(s);
|
||||||
|
break;
|
||||||
|
case A_TIMER1INTCLR:
|
||||||
|
m->intstatus = 0;
|
||||||
|
cmsdk_apb_dualtimer_update(s);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
goto bad_offset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const MemoryRegionOps cmsdk_apb_dualtimer_ops = {
|
||||||
|
.read = cmsdk_apb_dualtimer_read,
|
||||||
|
.write = cmsdk_apb_dualtimer_write,
|
||||||
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
|
/* byte/halfword accesses are just zero-padded on reads and writes */
|
||||||
|
.impl.min_access_size = 4,
|
||||||
|
.impl.max_access_size = 4,
|
||||||
|
.valid.min_access_size = 1,
|
||||||
|
.valid.max_access_size = 4,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void cmsdk_dualtimermod_tick(void *opaque)
|
||||||
|
{
|
||||||
|
CMSDKAPBDualTimerModule *m = opaque;
|
||||||
|
|
||||||
|
m->intstatus = 1;
|
||||||
|
cmsdk_apb_dualtimer_update(m->parent);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m)
|
||||||
|
{
|
||||||
|
m->control = R_CONTROL_INTEN_MASK;
|
||||||
|
m->intstatus = 0;
|
||||||
|
m->load = 0;
|
||||||
|
m->value = 0xffffffff;
|
||||||
|
ptimer_stop(m->timer);
|
||||||
|
/*
|
||||||
|
* We start in free-running mode, with VALUE at 0xffffffff, and
|
||||||
|
* in 16-bit counter mode. This means that the ptimer count and
|
||||||
|
* limit must both be set to 0xffff, so we wrap at 16 bits.
|
||||||
|
*/
|
||||||
|
ptimer_set_limit(m->timer, 0xffff, 1);
|
||||||
|
ptimer_set_freq(m->timer, m->parent->pclk_frq);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void cmsdk_apb_dualtimer_reset(DeviceState *dev)
|
||||||
|
{
|
||||||
|
CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
trace_cmsdk_apb_dualtimer_reset();
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
|
||||||
|
cmsdk_dualtimermod_reset(&s->timermod[i]);
|
||||||
|
}
|
||||||
|
s->timeritcr = 0;
|
||||||
|
s->timeritop = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void cmsdk_apb_dualtimer_init(Object *obj)
|
||||||
|
{
|
||||||
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||||
|
CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(obj);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
memory_region_init_io(&s->iomem, obj, &cmsdk_apb_dualtimer_ops,
|
||||||
|
s, "cmsdk-apb-dualtimer", 0x1000);
|
||||||
|
sysbus_init_mmio(sbd, &s->iomem);
|
||||||
|
sysbus_init_irq(sbd, &s->timerintc);
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
|
||||||
|
sysbus_init_irq(sbd, &s->timermod[i].timerint);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
|
||||||
|
{
|
||||||
|
CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (s->pclk_frq == 0) {
|
||||||
|
error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
|
||||||
|
CMSDKAPBDualTimerModule *m = &s->timermod[i];
|
||||||
|
QEMUBH *bh = qemu_bh_new(cmsdk_dualtimermod_tick, m);
|
||||||
|
|
||||||
|
m->parent = s;
|
||||||
|
m->timer = ptimer_init(bh,
|
||||||
|
PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
|
||||||
|
PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
|
||||||
|
PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
|
||||||
|
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription cmsdk_dualtimermod_vmstate = {
|
||||||
|
.name = "cmsdk-apb-dualtimer-module",
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_PTIMER(timer, CMSDKAPBDualTimerModule),
|
||||||
|
VMSTATE_UINT32(load, CMSDKAPBDualTimerModule),
|
||||||
|
VMSTATE_UINT32(value, CMSDKAPBDualTimerModule),
|
||||||
|
VMSTATE_UINT32(control, CMSDKAPBDualTimerModule),
|
||||||
|
VMSTATE_UINT32(intstatus, CMSDKAPBDualTimerModule),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
|
||||||
|
.name = "cmsdk-apb-dualtimer",
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer,
|
||||||
|
CMSDK_APB_DUALTIMER_NUM_MODULES,
|
||||||
|
1, cmsdk_dualtimermod_vmstate,
|
||||||
|
CMSDKAPBDualTimerModule),
|
||||||
|
VMSTATE_UINT32(timeritcr, CMSDKAPBDualTimer),
|
||||||
|
VMSTATE_UINT32(timeritop, CMSDKAPBDualTimer),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static Property cmsdk_apb_dualtimer_properties[] = {
|
||||||
|
DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0),
|
||||||
|
DEFINE_PROP_END_OF_LIST(),
|
||||||
|
};
|
||||||
|
|
||||||
|
static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
|
||||||
|
{
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||||
|
|
||||||
|
dc->realize = cmsdk_apb_dualtimer_realize;
|
||||||
|
dc->vmsd = &cmsdk_apb_dualtimer_vmstate;
|
||||||
|
dc->reset = cmsdk_apb_dualtimer_reset;
|
||||||
|
dc->props = cmsdk_apb_dualtimer_properties;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TypeInfo cmsdk_apb_dualtimer_info = {
|
||||||
|
.name = TYPE_CMSDK_APB_DUALTIMER,
|
||||||
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||||||
|
.instance_size = sizeof(CMSDKAPBDualTimer),
|
||||||
|
.instance_init = cmsdk_apb_dualtimer_init,
|
||||||
|
.class_init = cmsdk_apb_dualtimer_class_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void cmsdk_apb_dualtimer_register_types(void)
|
||||||
|
{
|
||||||
|
type_register_static(&cmsdk_apb_dualtimer_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(cmsdk_apb_dualtimer_register_types);
|
||||||
@ -61,5 +61,10 @@ cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB t
|
|||||||
cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||||
cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset"
|
cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset"
|
||||||
|
|
||||||
|
# hw/timer/cmsdk_apb_dualtimer.c
|
||||||
|
cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||||
|
cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||||
|
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
|
||||||
|
|
||||||
# hw/timer/xlnx-zynqmp-rtc.c
|
# hw/timer/xlnx-zynqmp-rtc.c
|
||||||
xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d"
|
xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d"
|
||||||
|
|||||||
72
include/hw/timer/cmsdk-apb-dualtimer.h
Normal file
72
include/hw/timer/cmsdk-apb-dualtimer.h
Normal file
@ -0,0 +1,72 @@
|
|||||||
|
/*
|
||||||
|
* ARM CMSDK APB dual-timer emulation
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 Linaro Limited
|
||||||
|
* Written by Peter Maydell
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This is a model of the "APB dual-input timer" which is part of the Cortex-M
|
||||||
|
* System Design Kit (CMSDK) and documented in the Cortex-M System
|
||||||
|
* Design Kit Technical Reference Manual (ARM DDI0479C):
|
||||||
|
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
|
||||||
|
*
|
||||||
|
* QEMU interface:
|
||||||
|
* + QOM property "pclk-frq": frequency at which the timer is clocked
|
||||||
|
* + sysbus MMIO region 0: the register bank
|
||||||
|
* + sysbus IRQ 0: combined timer interrupt TIMINTC
|
||||||
|
* + sysbus IRO 1: timer block 1 interrupt TIMINT1
|
||||||
|
* + sysbus IRQ 2: timer block 2 interrupt TIMINT2
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CMSDK_APB_DUALTIMER_H
|
||||||
|
#define CMSDK_APB_DUALTIMER_H
|
||||||
|
|
||||||
|
#include "hw/sysbus.h"
|
||||||
|
#include "hw/ptimer.h"
|
||||||
|
|
||||||
|
#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
|
||||||
|
#define CMSDK_APB_DUALTIMER(obj) OBJECT_CHECK(CMSDKAPBDualTimer, (obj), \
|
||||||
|
TYPE_CMSDK_APB_DUALTIMER)
|
||||||
|
|
||||||
|
typedef struct CMSDKAPBDualTimer CMSDKAPBDualTimer;
|
||||||
|
|
||||||
|
/* One of the two identical timer modules in the dual-timer module */
|
||||||
|
typedef struct CMSDKAPBDualTimerModule {
|
||||||
|
CMSDKAPBDualTimer *parent;
|
||||||
|
struct ptimer_state *timer;
|
||||||
|
qemu_irq timerint;
|
||||||
|
/*
|
||||||
|
* We must track the guest LOAD and VALUE register state by hand
|
||||||
|
* rather than leaving this state only in the ptimer limit/count,
|
||||||
|
* because if CONTROL.SIZE is 0 then only the low 16 bits of the
|
||||||
|
* counter actually counts, but the high half is still guest
|
||||||
|
* accessible.
|
||||||
|
*/
|
||||||
|
uint32_t load;
|
||||||
|
uint32_t value;
|
||||||
|
uint32_t control;
|
||||||
|
uint32_t intstatus;
|
||||||
|
} CMSDKAPBDualTimerModule;
|
||||||
|
|
||||||
|
#define CMSDK_APB_DUALTIMER_NUM_MODULES 2
|
||||||
|
|
||||||
|
struct CMSDKAPBDualTimer {
|
||||||
|
/*< private >*/
|
||||||
|
SysBusDevice parent_obj;
|
||||||
|
|
||||||
|
/*< public >*/
|
||||||
|
MemoryRegion iomem;
|
||||||
|
qemu_irq timerintc;
|
||||||
|
uint32_t pclk_frq;
|
||||||
|
|
||||||
|
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
|
||||||
|
uint32_t timeritcr;
|
||||||
|
uint32_t timeritop;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue
Block a user