From 4f2493146d783d71c5dc6e72452f80b86641ba7f Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Tue, 7 Mar 2023 19:07:08 +0100 Subject: [PATCH] target/riscv: redirect XVentanaCondOps to use the Zicond functions The Zicond standard extension implements the same instruction semantics as XVentanaCondOps, although using different mnemonics and opcodes. Point XVentanaCondOps to the (newly implemented) Zicond implementation to reduce the future maintenance burden. Also updating MAINTAINERS as trans_xventanacondops.c.inc. Reviewed-by: Richard Henderson Signed-off-by: Philipp Tomsich Acked-by: Alistair Francis Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- MAINTAINERS | 2 +- .../insn_trans/trans_xventanacondops.c.inc | 18 +++--------------- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b22b85bc3a..431556c217 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -328,7 +328,7 @@ F: target/riscv/xthead*.decode RISC-V XVentanaCondOps extension M: Philipp Tomsich L: qemu-riscv@nongnu.org -S: Supported +S: Maintained F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc index 16849e6d4e..38c15f2825 100644 --- a/target/riscv/insn_trans/trans_xventanacondops.c.inc +++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc @@ -1,7 +1,7 @@ /* * RISC-V translation routines for the XVentanaCondOps extension. * - * Copyright (c) 2021-2022 VRULL GmbH. + * Copyright (c) 2021-2023 VRULL GmbH. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,24 +16,12 @@ * this program. If not, see . */ -static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond) -{ - TCGv dest = dest_gpr(ctx, a->rd); - TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); - TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); - - tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero); - - gen_set_gpr(ctx, a->rd, dest); - return true; -} - static bool trans_vt_maskc(DisasContext *ctx, arg_r *a) { - return gen_vt_condmask(ctx, a, TCG_COND_NE); + return gen_logic(ctx, a, gen_czero_eqz); } static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a) { - return gen_vt_condmask(ctx, a, TCG_COND_EQ); + return gen_logic(ctx, a, gen_czero_nez); }