target-xtensa: implement FP1 group

These are comparison and conditional move opcodes.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Max Filippov 2012-09-19 04:23:58 +04:00 committed by Blue Swirl
parent b7ee8c6a32
commit 4e27386967
3 changed files with 135 additions and 1 deletions

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@ -49,4 +49,12 @@ DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32)
DEF_HELPER_3(itof, f32, env, i32, i32)
DEF_HELPER_3(uitof, f32, env, i32, i32)
DEF_HELPER_4(un_s, void, env, i32, f32, f32)
DEF_HELPER_4(oeq_s, void, env, i32, f32, f32)
DEF_HELPER_4(ueq_s, void, env, i32, f32, f32)
DEF_HELPER_4(olt_s, void, env, i32, f32, f32)
DEF_HELPER_4(ult_s, void, env, i32, f32, f32)
DEF_HELPER_4(ole_s, void, env, i32, f32, f32)
DEF_HELPER_4(ule_s, void, env, i32, f32, f32)
#include "def-helper.h"

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@ -858,3 +858,50 @@ float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
return float32_scalbn(uint32_to_float32(v, &env->fp_status),
(int32_t)scale, &env->fp_status);
}
static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
{
if (v) {
env->sregs[BR] |= br;
} else {
env->sregs[BR] &= ~br;
}
}
void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
{
set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
}
void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
{
set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
}
void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
{
int v = float32_compare_quiet(a, b, &env->fp_status);
set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
}
void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
{
set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
}
void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
{
int v = float32_compare_quiet(a, b, &env->fp_status);
set_br(env, v == float_relation_less || v == float_relation_unordered, br);
}
void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
{
set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
}
void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
{
int v = float32_compare_quiet(a, b, &env->fp_status);
set_br(env, v != float_relation_greater, br);
}

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@ -2019,7 +2019,86 @@ static void disas_xtensa_insn(DisasContext *dc)
case 11: /*FP1*/
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
TBD();
#define gen_compare(rel, br, a, b) \
do { \
TCGv_i32 bit = tcg_const_i32(1 << br); \
\
gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
tcg_temp_free(bit); \
} while (0)
switch (OP2) {
case 1: /*UN.Sf*/
gen_compare(un_s, RRR_R, RRR_S, RRR_T);
break;
case 2: /*OEQ.Sf*/
gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
break;
case 3: /*UEQ.Sf*/
gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
break;
case 4: /*OLT.Sf*/
gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
break;
case 5: /*ULT.Sf*/
gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
break;
case 6: /*OLE.Sf*/
gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
break;
case 7: /*ULE.Sf*/
gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
break;
#undef gen_compare
case 8: /*MOVEQZ.Sf*/
case 9: /*MOVNEZ.Sf*/
case 10: /*MOVLTZ.Sf*/
case 11: /*MOVGEZ.Sf*/
gen_window_check1(dc, RRR_T);
{
static const TCGCond cond[] = {
TCG_COND_NE,
TCG_COND_EQ,
TCG_COND_GE,
TCG_COND_LT
};
int label = gen_new_label();
tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
gen_set_label(label);
}
break;
case 12: /*MOVF.Sf*/
case 13: /*MOVT.Sf*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
{
int label = gen_new_label();
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
tcg_gen_brcondi_i32(
OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
tmp, 0, label);
tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
gen_set_label(label);
tcg_temp_free(tmp);
}
break;
default: /*reserved*/
RESERVED();
break;
}
break;
default: /*reserved*/