docs/specs/edu: Convert to rST
Convert docs/specs/edu.txt to rST format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20230927151205.70930-3-peter.maydell@linaro.org
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Peter Maydell
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@ -1882,6 +1882,7 @@ EDU
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M: Jiri Slaby <jslaby@suse.cz>
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S: Maintained
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F: hw/misc/edu.c
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F: docs/specs/edu.rst
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IDE
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M: John Snow <jsnow@redhat.com>
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@ -2,9 +2,10 @@
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EDU device
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==========
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Copyright (c) 2014-2015 Jiri Slaby
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..
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Copyright (c) 2014-2015 Jiri Slaby
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This document is licensed under the GPLv2 (or later).
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This document is licensed under the GPLv2 (or later).
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This is an educational device for writing (kernel) drivers. Its original
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intention was to support the Linux kernel lectures taught at the Masaryk
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@ -15,10 +16,11 @@ The devices behaves very similar to the PCI bridge present in the COMBO6 cards
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developed under the Liberouter wings. Both PCI device ID and PCI space is
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inherited from that device.
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Command line switches:
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-device edu[,dma_mask=mask]
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Command line switches
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---------------------
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dma_mask makes the virtual device work with DMA addresses with the given
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``-device edu[,dma_mask=mask]``
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``dma_mask`` makes the virtual device work with DMA addresses with the given
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mask. For educational purposes, the device supports only 28 bits (256 MiB)
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by default. Students shall set dma_mask for the device in the OS driver
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properly.
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@ -26,7 +28,8 @@ Command line switches:
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PCI specs
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---------
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PCI ID: 1234:11e8
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PCI ID:
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``1234:11e8``
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PCI Region 0:
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I/O memory, 1 MB in size. Users are supposed to communicate with the card
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@ -35,24 +38,29 @@ PCI Region 0:
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MMIO area spec
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--------------
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Only size == 4 accesses are allowed for addresses < 0x80. size == 4 or
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size == 8 for the rest.
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Only ``size == 4`` accesses are allowed for addresses ``< 0x80``.
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``size == 4`` or ``size == 8`` for the rest.
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0x00 (RO) : identification (0xRRrr00edu)
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RR -- major version
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rr -- minor version
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0x00 (RO) : identification
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Value is in the form ``0xRRrr00edu`` where:
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- ``RR`` -- major version
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- ``rr`` -- minor version
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0x04 (RW) : card liveness check
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It is a simple value inversion (~ C operator).
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It is a simple value inversion (``~`` C operator).
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0x08 (RW) : factorial computation
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The stored value is taken and factorial of it is put back here.
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This happens only after factorial bit in the status register (0x20
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below) is cleared.
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0x20 (RW) : status register, bitwise OR
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0x01 -- computing factorial (RO)
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0x80 -- raise interrupt after finishing factorial computation
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0x20 (RW) : status register
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Bitwise OR of:
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0x01
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computing factorial (RO)
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0x80
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raise interrupt after finishing factorial computation
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0x24 (RO) : interrupt status register
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It contains values which raised the interrupt (see interrupt raise
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@ -76,13 +84,19 @@ size == 8 for the rest.
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0x90 (RW) : DMA transfer count
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The size of the area to perform the DMA on.
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0x98 (RW) : DMA command register, bitwise OR
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0x01 -- start transfer
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0x02 -- direction (0: from RAM to EDU, 1: from EDU to RAM)
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0x04 -- raise interrupt 0x100 after finishing the DMA
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0x98 (RW) : DMA command register
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Bitwise OR of:
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0x01
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start transfer
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0x02
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direction (0: from RAM to EDU, 1: from EDU to RAM)
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0x04
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raise interrupt 0x100 after finishing the DMA
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IRQ controller
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--------------
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An IRQ is generated when written to the interrupt raise register. The value
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appears in interrupt status register when the interrupt is raised and has to
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be written to the interrupt acknowledge register to lower it.
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@ -94,22 +108,28 @@ routine.
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DMA controller
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--------------
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One has to specify, source, destination, size, and start the transfer. One
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4096 bytes long buffer at offset 0x40000 is available in the EDU device. I.e.
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one can perform DMA to/from this space when programmed properly.
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Example of transferring a 100 byte block to and from the buffer using a given
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PCI address 'addr':
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addr -> DMA source address
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0x40000 -> DMA destination address
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100 -> DMA transfer count
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1 -> DMA command register
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while (DMA command register & 1)
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PCI address ``addr``:
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::
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addr -> DMA source address
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0x40000 -> DMA destination address
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100 -> DMA transfer count
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1 -> DMA command register
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while (DMA command register & 1)
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;
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0x40000 -> DMA source address
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addr+100 -> DMA destination address
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100 -> DMA transfer count
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3 -> DMA command register
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while (DMA command register & 1)
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::
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0x40000 -> DMA source address
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addr+100 -> DMA destination address
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100 -> DMA transfer count
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3 -> DMA command register
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while (DMA command register & 1)
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;
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@ -25,3 +25,4 @@ guest hardware that is specific to QEMU.
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sev-guest-firmware
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fw_cfg
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vmw_pvscsi-spec
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edu
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