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tcg: spelling fixes

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Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20230823065335.1919380-4-mjt@tls.msk.ru>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Michael Tokarev 2023-08-23 09:53:16 +03:00 committed by Richard Henderson
parent b08caa6d50
commit 4daad8d9d6
3 changed files with 9 additions and 7 deletions
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2
tcg/aarch64/tcg-target.c.inc
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@ -3098,7 +3098,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
#if !defined(CONFIG_SOFTMMU)
/*
* Note that XZR cannot be encoded in the address base register slot,
* as that actaully encodes SP. Depending on the guest, we may need
* as that actually encodes SP. Depending on the guest, we may need
* to zero-extend the guest address via the address index register slot,
* therefore we need to load even a zero guest base into a register.
*/

10
tcg/arm/tcg-target.c.inc
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@ -1216,9 +1216,11 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
case TCG_COND_LEU:
case TCG_COND_GTU:
case TCG_COND_GEU:
/* We perform a conditional comparision. If the high half is
equal, then overwrite the flags with the comparison of the
low half. The resulting flags cover the whole. */
/*
* We perform a conditional comparison. If the high half is
* equal, then overwrite the flags with the comparison of the
* low half. The resulting flags cover the whole.
*/
tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh);
tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl);
return cond;
@ -1250,7 +1252,7 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
/*
* Note that TCGReg references Q-registers.
* Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
* Q-regno = 2 * D-regno, so shift left by 1 while inserting.
*/
static uint32_t encode_vd(TCGReg rd)
{

4
tcg/riscv/tcg-target.c.inc
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@ -69,7 +69,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers */
/* TCG_REG_S0 reservered for TCG_AREG0 */
/* TCG_REG_S0 reserved for TCG_AREG0 */
TCG_REG_S1,
TCG_REG_S2,
TCG_REG_S3,
@ -260,7 +260,7 @@ typedef enum {
/* Zba: Bit manipulation extension, address generation */
OPC_ADD_UW = 0x0800003b,
/* Zbb: Bit manipulation extension, basic bit manipulaton */
/* Zbb: Bit manipulation extension, basic bit manipulation */
OPC_ANDN = 0x40007033,
OPC_CLZ = 0x60001013,
OPC_CLZW = 0x6000101b,