From 4da0033e6ead7921dada84a3321e35f287db6887 Mon Sep 17 00:00:00 2001 From: aurel32 Date: Sun, 2 Nov 2008 08:22:16 +0000 Subject: [PATCH] target-ppc: fix srw on 64-bit targets Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5595 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-ppc/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index e003761d6a..d45b607a65 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2012,7 +2012,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) /* srw & srw. */ GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) { - TCGv temp; + TCGv temp, temp2; int l1, l2; l1 = gen_new_label(); l2 = gen_new_label(); @@ -2024,8 +2024,10 @@ GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) tcg_gen_br(l2); gen_set_label(l1); tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + temp2 = tcg_temp_new(TCG_TYPE_TL); + tcg_gen_ext32u_tl(temp2, cpu_gpr[rS(ctx->opcode)]); + tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], temp2, temp); + tcg_temp_free(temp2); gen_set_label(l2); tcg_temp_free(temp); if (unlikely(Rc(ctx->opcode) != 0))