From 4c759943ec23bca891ad25fb2a9988f1b78f9e7d Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Thu, 6 Apr 2023 15:03:36 -0300 Subject: [PATCH] target/riscv: remove cpu->cfg.ext_a Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 16 ++++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b234a03d0..3770fd4f6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && + riscv_has_ext(env, RVA) && + cpu->cfg.ext_f && cpu->cfg.ext_d && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i = true; cpu->cfg.ext_m = true; - cpu->cfg.ext_a = true; cpu->cfg.ext_f = true; cpu->cfg.ext_d = true; cpu->cfg.ext_icsr = true; @@ -869,7 +868,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1160,7 +1159,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_cpu_cfg(env)->ext_m) { ext |= RVM; } - if (riscv_cpu_cfg(env)->ext_a) { + if (riscv_has_ext(env, RVA)) { ext |= RVA; } if (riscv_cpu_cfg(env)->ext_f) { @@ -1496,7 +1495,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, visit_type_bool(v, name, &value, errp); } -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {}; +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { + {.name = "a", .description = "Atomic instructions", + .misa_bit = RVA, .enabled = true}, +}; static void riscv_cpu_add_misa_properties(Object *cpu_obj) { @@ -1522,7 +1524,6 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i = misa_ext & RVI; cpu->cfg.ext_e = misa_ext & RVE; cpu->cfg.ext_m = misa_ext & RVM; - cpu->cfg.ext_a = misa_ext & RVA; cpu->cfg.ext_f = misa_ext & RVF; cpu->cfg.ext_d = misa_ext & RVD; cpu->cfg.ext_v = misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cbf3de2708..1d1a17d85b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,7 +426,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_a; bool ext_f; bool ext_d; bool ext_c;