net: cadence_gem: Define access permission for interrupt registers
Q1 to Q7 ISR's are clear-on-read, IER/IDR registers are write-only, mask reg are read-only. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
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@ -458,6 +458,7 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
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*/
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static void gem_init_register_masks(CadenceGEMState *s)
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{
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unsigned int i;
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/* Mask of register bits which are read only */
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memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
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s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
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@ -470,10 +471,19 @@ static void gem_init_register_masks(CadenceGEMState *s)
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s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
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s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
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s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
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for (i = 0; i < s->num_priority_queues; i++) {
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s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF;
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s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319;
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s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319;
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s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF;
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}
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/* Mask of register bits which are clear on read */
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memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
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s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
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for (i = 0; i < s->num_priority_queues; i++) {
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s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6;
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}
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/* Mask of register bits which are write 1 to clear */
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memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
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@ -485,6 +495,10 @@ static void gem_init_register_masks(CadenceGEMState *s)
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s->regs_wo[GEM_NWCTRL] = 0x00073E60;
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s->regs_wo[GEM_IER] = 0x07FFFFFF;
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s->regs_wo[GEM_IDR] = 0x07FFFFFF;
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for (i = 0; i < s->num_priority_queues; i++) {
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s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6;
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s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6;
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}
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}
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/*
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