target/hppa: Rename cond_make_* helpers
Use 'v' for a variable that needs copying, 't' for a temp that doesn't need copying, and 'i' for an immediate, and use this naming for both arguments of the comparison. So: cond_make_tmp -> cond_make_tt cond_make_0_tmp -> cond_make_ti cond_make_0 -> cond_make_vi cond_make -> cond_make_vv Pass 0 explictly, rather than implicitly in the function name. Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -345,32 +345,32 @@ static DisasCond cond_make_n(void)
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};
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}
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static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
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static DisasCond cond_make_tt(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
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{
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assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
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return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 };
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}
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static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0)
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static DisasCond cond_make_ti(TCGCond c, TCGv_i64 a0, uint64_t imm)
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{
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return cond_make_tmp(c, a0, tcg_constant_i64(0));
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return cond_make_tt(c, a0, tcg_constant_i64(imm));
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}
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static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0)
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static DisasCond cond_make_vi(TCGCond c, TCGv_i64 a0, uint64_t imm)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_mov_i64(tmp, a0);
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return cond_make_0_tmp(c, tmp);
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return cond_make_ti(c, tmp, imm);
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}
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static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
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static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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tcg_gen_mov_i64(t0, a0);
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tcg_gen_mov_i64(t1, a1);
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return cond_make_tmp(c, t0, t1);
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return cond_make_tt(c, t0, t1);
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}
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static void cond_free(DisasCond *cond)
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@ -789,7 +789,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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tcg_gen_ext32u_i64(tmp, res);
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res = tmp;
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}
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cond = cond_make_0(TCG_COND_EQ, res);
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cond = cond_make_vi(TCG_COND_EQ, res, 0);
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break;
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case 2: /* < / >= (N ^ V / !(N ^ V) */
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tmp = tcg_temp_new_i64();
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@ -797,7 +797,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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if (!d) {
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tcg_gen_ext32s_i64(tmp, tmp);
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}
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cond = cond_make_0_tmp(TCG_COND_LT, tmp);
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cond = cond_make_ti(TCG_COND_LT, tmp, 0);
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break;
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case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
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/*
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@ -819,10 +819,10 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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tcg_gen_sari_i64(tmp, tmp, 63);
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tcg_gen_and_i64(tmp, tmp, res);
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}
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cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
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cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
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break;
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case 4: /* NUV / UV (!UV / UV) */
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cond = cond_make_0(TCG_COND_EQ, uv);
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cond = cond_make_vi(TCG_COND_EQ, uv, 0);
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break;
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case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */
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tmp = tcg_temp_new_i64();
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@ -830,7 +830,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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if (!d) {
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tcg_gen_ext32u_i64(tmp, tmp);
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}
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cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
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cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
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break;
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case 6: /* SV / NSV (V / !V) */
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if (!d) {
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@ -838,12 +838,12 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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tcg_gen_ext32s_i64(tmp, sv);
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sv = tmp;
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}
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cond = cond_make_0(TCG_COND_LT, sv);
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cond = cond_make_ti(TCG_COND_LT, sv, 0);
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break;
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case 7: /* OD / EV */
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tmp = tcg_temp_new_i64();
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tcg_gen_andi_i64(tmp, res, 1);
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cond = cond_make_0_tmp(TCG_COND_NE, tmp);
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cond = cond_make_ti(TCG_COND_NE, tmp, 0);
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break;
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default:
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g_assert_not_reached();
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@ -905,9 +905,9 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
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tcg_gen_ext32s_i64(t1, in1);
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tcg_gen_ext32s_i64(t2, in2);
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}
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return cond_make_tmp(tc, t1, t2);
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return cond_make_tt(tc, t1, t2);
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}
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return cond_make(tc, in1, in2);
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return cond_make_vv(tc, in1, in2);
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}
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/*
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@ -979,9 +979,9 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
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} else {
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tcg_gen_ext32s_i64(tmp, res);
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}
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return cond_make_0_tmp(tc, tmp);
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return cond_make_ti(tc, tmp, 0);
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}
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return cond_make_0(tc, res);
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return cond_make_vi(tc, res, 0);
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}
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/* Similar, but for shift/extract/deposit conditions. */
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@ -1040,7 +1040,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res)
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tcg_gen_andc_i64(tmp, tmp, res);
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tcg_gen_andi_i64(tmp, tmp, sgns);
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return cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp);
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return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0);
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}
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static TCGv_i64 get_carry(DisasContext *ctx, bool d,
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@ -1454,7 +1454,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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}
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tcg_gen_andi_i64(cb, cb, test_cb);
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cond = cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb);
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cond = cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb, 0);
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}
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if (is_tc) {
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@ -3543,7 +3543,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
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tcg_gen_shl_i64(tmp, tcg_r, tmp);
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}
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cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
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cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0);
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return do_cbranch(ctx, a->disp, a->n, &cond);
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}
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@ -3560,7 +3560,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
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p = a->p | (a->d ? 0 : 32);
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tcg_gen_shli_i64(tmp, tcg_r, p);
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cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
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cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0);
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return do_cbranch(ctx, a->disp, a->n, &cond);
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}
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@ -4364,7 +4364,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
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switch (a->c) {
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case 0: /* simple */
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tcg_gen_andi_i64(t, t, 0x4000000);
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ctx->null_cond = cond_make_0(TCG_COND_NE, t);
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ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0);
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goto done;
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case 2: /* rej */
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inv = true;
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@ -4394,16 +4394,16 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
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if (inv) {
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TCGv_i64 c = tcg_constant_i64(mask);
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tcg_gen_or_i64(t, t, c);
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ctx->null_cond = cond_make(TCG_COND_EQ, t, c);
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ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c);
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} else {
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tcg_gen_andi_i64(t, t, mask);
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ctx->null_cond = cond_make_0(TCG_COND_EQ, t);
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ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0);
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}
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} else {
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unsigned cbit = (a->y ^ 1) - 1;
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tcg_gen_extract_i64(t, t, 21 - cbit, 1);
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ctx->null_cond = cond_make_0(TCG_COND_NE, t);
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ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0);
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}
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done:
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