hw/isa/superio: Factor out the parallel code from pc87312.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180308223946.26784-11-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -10,14 +10,79 @@
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* SPDX-License-Identifier: GPL-2.0-or-later
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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*/
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "sysemu/sysemu.h"
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#include "chardev/char.h"
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#include "hw/isa/superio.h"
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#include "hw/isa/superio.h"
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#include "trace.h"
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#include "trace.h"
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static void isa_superio_realize(DeviceState *dev, Error **errp)
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{
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ISASuperIODevice *sio = ISA_SUPERIO(dev);
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ISASuperIOClass *k = ISA_SUPERIO_GET_CLASS(sio);
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ISABus *bus = isa_bus_from_device(ISA_DEVICE(dev));
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ISADevice *isa;
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DeviceState *d;
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Chardev *chr;
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char *name;
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int i;
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/* Parallel port */
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for (i = 0; i < k->parallel.count; i++) {
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if (i >= ARRAY_SIZE(sio->parallel)) {
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warn_report("superio: ignoring %td parallel controllers",
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k->parallel.count - ARRAY_SIZE(sio->parallel));
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break;
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}
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if (!k->parallel.is_enabled || k->parallel.is_enabled(sio, i)) {
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/* FIXME use a qdev chardev prop instead of parallel_hds[] */
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chr = parallel_hds[i];
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if (chr == NULL || chr->be) {
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name = g_strdup_printf("discarding-parallel%d", i);
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chr = qemu_chr_new(name, "null");
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} else {
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name = g_strdup_printf("parallel%d", i);
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}
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isa = isa_create(bus, "isa-parallel");
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d = DEVICE(isa);
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qdev_prop_set_uint32(d, "index", i);
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if (k->parallel.get_iobase) {
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qdev_prop_set_uint32(d, "iobase",
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k->parallel.get_iobase(sio, i));
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}
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if (k->parallel.get_irq) {
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qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i));
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}
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qdev_prop_set_chr(d, "chardev", chr);
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qdev_init_nofail(d);
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sio->parallel[i] = isa;
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trace_superio_create_parallel(i,
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k->parallel.get_iobase ?
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k->parallel.get_iobase(sio, i) : -1,
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k->parallel.get_irq ?
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k->parallel.get_irq(sio, i) : -1);
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object_property_add_child(OBJECT(dev), name,
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OBJECT(sio->parallel[i]), NULL);
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g_free(name);
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}
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}
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}
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static void isa_superio_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = isa_superio_realize;
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/* Reason: Uses parallel_hds[0] in realize(), so it can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo isa_superio_type_info = {
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static const TypeInfo isa_superio_type_info = {
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.name = TYPE_ISA_SUPERIO,
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.name = TYPE_ISA_SUPERIO,
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.parent = TYPE_ISA_DEVICE,
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.parent = TYPE_ISA_DEVICE,
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.abstract = true,
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.abstract = true,
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.class_size = sizeof(ISASuperIOClass),
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.class_size = sizeof(ISASuperIOClass),
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.class_init = isa_superio_class_init,
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};
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};
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static void isa_superio_register_types(void)
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static void isa_superio_register_types(void)
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@ -64,22 +64,25 @@
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/* Parallel port */
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/* Parallel port */
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static inline bool is_parallel_enabled(PC87312State *s)
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static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index)
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{
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{
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return s->regs[REG_FER] & FER_PARALLEL_EN;
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PC87312State *s = PC87312(sio);
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return index ? false : s->regs[REG_FER] & FER_PARALLEL_EN;
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}
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}
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static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
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static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
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static inline uint16_t get_parallel_iobase(PC87312State *s)
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static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index)
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{
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{
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PC87312State *s = PC87312(sio);
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return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
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return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
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}
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}
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static const unsigned int parallel_irq[] = { 5, 7, 5, 0 };
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static const unsigned int parallel_irq[] = { 5, 7, 5, 0 };
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static inline unsigned int get_parallel_irq(PC87312State *s)
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static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index)
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{
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{
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PC87312State *s = PC87312(sio);
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int idx;
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int idx;
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idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
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idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
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if (idx == 0) {
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if (idx == 0) {
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@ -286,24 +289,6 @@ static void pc87312_realize(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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if (is_parallel_enabled(s)) {
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/* FIXME use a qdev chardev prop instead of parallel_hds[] */
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chr = parallel_hds[0];
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if (chr == NULL) {
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chr = qemu_chr_new("par0", "null");
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}
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isa = isa_create(bus, "isa-parallel");
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d = DEVICE(isa);
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qdev_prop_set_uint32(d, "index", 0);
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qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s));
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qdev_prop_set_uint32(d, "irq", get_parallel_irq(s));
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qdev_prop_set_chr(d, "chardev", chr);
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qdev_init_nofail(d);
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s->parallel.dev = isa;
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trace_pc87312_info_parallel(get_parallel_iobase(s),
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get_parallel_irq(s));
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}
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for (i = 0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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if (is_uart_enabled(s, i)) {
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if (is_uart_enabled(s, i)) {
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/* FIXME use a qdev chardev prop instead of serial_hds[] */
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/* FIXME use a qdev chardev prop instead of serial_hds[] */
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@ -395,8 +380,15 @@ static void pc87312_class_init(ObjectClass *klass, void *data)
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dc->reset = pc87312_reset;
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dc->reset = pc87312_reset;
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dc->vmsd = &vmstate_pc87312;
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dc->vmsd = &vmstate_pc87312;
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dc->props = pc87312_properties;
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dc->props = pc87312_properties;
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/* Reason: Uses parallel_hds[0] in realize(), so it can't be used twice */
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/* Reason: Uses serial_hds[0] in realize(), so it can't be used twice */
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dc->user_creatable = false;
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dc->user_creatable = false;
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sc->parallel = (ISASuperIOFuncs){
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.count = 1,
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.is_enabled = is_parallel_enabled,
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.get_iobase = get_parallel_iobase,
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.get_irq = get_parallel_irq,
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};
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}
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}
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static const TypeInfo pc87312_type_info = {
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static const TypeInfo pc87312_type_info = {
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@ -1,9 +1,11 @@
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# See docs/devel/tracing.txt for syntax documentation.
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# See docs/devel/tracing.txt for syntax documentation.
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# hw/isa/isa-superio.c
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superio_create_parallel(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
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# hw/isa/pc87312.c
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# hw/isa/pc87312.c
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pc87312_io_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
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pc87312_io_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
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pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
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pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
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pc87312_info_floppy(uint32_t base) "base 0x%x"
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pc87312_info_floppy(uint32_t base) "base 0x%x"
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pc87312_info_ide(uint32_t base) "base 0x%x"
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pc87312_info_ide(uint32_t base) "base 0x%x"
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pc87312_info_parallel(uint32_t base, uint32_t irq) "base 0x%x, irq %u"
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pc87312_info_serial(int n, uint32_t base, uint32_t irq) "id=%d, base 0x%x, irq %u"
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pc87312_info_serial(int n, uint32_t base, uint32_t irq) "id=%d, base 0x%x, irq %u"
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@ -39,10 +39,6 @@ typedef struct PC87312State {
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uint16_t iobase;
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uint16_t iobase;
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uint8_t config; /* initial configuration */
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uint8_t config; /* initial configuration */
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struct {
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ISADevice *dev;
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} parallel;
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struct {
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struct {
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ISADevice *dev;
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ISADevice *dev;
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} uart[2];
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} uart[2];
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@ -23,7 +23,11 @@
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OBJECT_CLASS_CHECK(ISASuperIOClass, (klass), TYPE_ISA_SUPERIO)
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OBJECT_CLASS_CHECK(ISASuperIOClass, (klass), TYPE_ISA_SUPERIO)
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typedef struct ISASuperIODevice {
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typedef struct ISASuperIODevice {
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/*< private >*/
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ISADevice parent_obj;
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ISADevice parent_obj;
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/*< public >*/
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ISADevice *parallel[MAX_PARALLEL_PORTS];
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} ISASuperIODevice;
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} ISASuperIODevice;
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typedef struct ISASuperIOFuncs {
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typedef struct ISASuperIOFuncs {
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@ -39,6 +43,8 @@ typedef struct ISASuperIOClass {
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ISADeviceClass parent_class;
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ISADeviceClass parent_class;
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/*< public >*/
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceRealize parent_realize;
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ISASuperIOFuncs parallel;
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} ISASuperIOClass;
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} ISASuperIOClass;
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#endif /* HW_ISA_SUPERIO_H */
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#endif /* HW_ISA_SUPERIO_H */
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