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arm_pic: Pass ARMCPU to arm_pic_init_cpu()

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Pass it through to arm_pic_cpu_handler().

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Igor Mitsyanko <i.mitsyanko@samsung.com> (for exynos)
This commit is contained in:
Andreas Färber 2012-05-14 04:21:52 +02:00
parent 3aaa8dfae9
commit 4bd7466166
14 changed files with 21 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/arm-misc.h
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@ -16,7 +16,7 @@
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUARMState *env);
qemu_irq *arm_pic_init_cpu(ARMCPU *cpu);
/* armv7m.c */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,

8
hw/arm_pic.c
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@ -13,7 +13,9 @@
/* Input 0 is IRQ and input 1 is FIQ. */
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUARMState *env = (CPUARMState *)opaque;
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level)
@ -32,7 +34,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
}
}
qemu_irq *arm_pic_init_cpu(CPUARMState *env)
qemu_irq *arm_pic_init_cpu(ARMCPU *cpu)
{
return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
return qemu_allocate_irqs(arm_pic_cpu_handler, cpu, 2);
}

2
hw/armv7m.c
View File

@ -215,7 +215,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
nvic = qdev_create(NULL, "armv7m_nvic");
env->nvic = nvic;
qdev_init_nofail(nvic);
cpu_pic = arm_pic_init_cpu(env);
cpu_pic = arm_pic_init_cpu(cpu);
sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
for (i = 0; i < 64; i++) {
pic[i] = qdev_get_gpio_in(nvic, i);

3
hw/exynos4210.c
View File

@ -112,8 +112,9 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
fprintf(stderr, "Unable to find CPU %d definition\n", n);
exit(1);
}
/* Create PIC controller for each processor instance */
irqp = arm_pic_init_cpu(&s->cpu[n]->env);
irqp = arm_pic_init_cpu(s->cpu[n]);
/*
* Get GICs gpio_in cpu_irq to connect a combiner to them later.

5
hw/highbank.c
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@ -192,7 +192,6 @@ static void highbank_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUARMState *env = NULL;
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq *irqp;
@ -215,10 +214,10 @@ static void highbank_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
/* This will become a QOM property eventually */
cpu->reset_cbar = GIC_BASE_ADDR;
irqp = arm_pic_init_cpu(env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}

2
hw/integratorcp.c
View File

@ -476,7 +476,7 @@ static void integratorcp_init(ram_addr_t ram_size,
qdev_init_nofail(dev);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
cpu_pic = arm_pic_init_cpu(&cpu->env);
cpu_pic = arm_pic_init_cpu(cpu);
dev = sysbus_create_varargs("integrator_pic", 0x14000000,
cpu_pic[ARM_PIC_CPU_IRQ],
cpu_pic[ARM_PIC_CPU_FIQ], NULL);

2
hw/musicpal.c
View File

@ -1538,7 +1538,7 @@ static void musicpal_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
cpu_pic = arm_pic_init_cpu(&cpu->env);
cpu_pic = arm_pic_init_cpu(cpu);
/* For now we use a fixed - the original - RAM size */
memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);

2
hw/omap1.c
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@ -3854,7 +3854,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
cpu_irq = arm_pic_init_cpu(&s->cpu->env);
cpu_irq = arm_pic_init_cpu(s->cpu);
s->ih[0] = qdev_create(NULL, "omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));

2
hw/omap2.c
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@ -2277,7 +2277,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
cpu_irq = arm_pic_init_cpu(&s->cpu->env);
cpu_irq = arm_pic_init_cpu(s->cpu);
s->ih[0] = qdev_create(NULL, "omap2-intc");
qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));

2
hw/realview.c
View File

@ -94,7 +94,7 @@ static void realview_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(&cpu->env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
env = &cpu->env;

2
hw/strongarm.c
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@ -1574,7 +1574,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
pic = arm_pic_init_cpu(&s->cpu->env);
pic = arm_pic_init_cpu(s->cpu);
s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);

2
hw/versatilepb.c
View File

@ -209,7 +209,7 @@ static void versatile_init(ram_addr_t ram_size,
qdev_init_nofail(sysctl);
sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
cpu_pic = arm_pic_init_cpu(&cpu->env);
cpu_pic = arm_pic_init_cpu(cpu);
dev = sysbus_create_varargs("pl190", 0x10140000,
cpu_pic[0], cpu_pic[1], NULL);
for (n = 0; n < 32; n++) {

4
hw/vexpress.c
View File

@ -181,7 +181,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(&cpu->env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
@ -280,7 +280,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(&cpu->env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}

2
hw/xilinx_zynq.c
View File

@ -71,7 +71,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(&cpu->env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq = irqp[ARM_PIC_CPU_IRQ];
/* max 2GB ram */