qemu-sparc update
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJU/vQnAAoJEFvCxW+uDzIfSHQIAKLVePJyOEtVA5OOUSyuA5TQ 6MNXg1X+PxD0GT8iyKhcyHqaRSibPjY/D2Hb8MyNt/lLIQj13hfL1fXXAMvnjY1+ WcCpGfbZmmcIpgjY+OWkkSVU3nSxNE6a0ZgdOvK9Cvc+dJHMpO02E5kRqig6nYX6 UuA7aIgjE2T63PPucuEjFVA4a8v7NsqO4OBmYPO/L7KEpAQk3Y/qDDGahQRXuBXl 0poyJrj99BoKHJFemf7L79SbpZHrnaQ54dndqerq5tzmBXRVjhYJa/iLm0LSjPnN kWdlMKXSGgI/rFRWZqfOk+jDIZb21xliM6y/lDpDJGdoC1aPsIWwQ0mFK6ZPVDo= =Ee+Y -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging qemu-sparc update # gpg: Signature made Tue Mar 10 13:39:51 2015 GMT using RSA key ID AE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" * remotes/mcayland/tags/qemu-sparc-signed: sun4u: switch m48t59 NVRAM to MMIO access MAINTAINERS: add myself as SPARC maintainer doc: minor updates to SPARC32 and SPARC64 documentation m48t59: add m48t59 sysbus device m48t59: introduce new base-year qdev property m48t59: let init functions return a Nvram object m48t59: add a Nvram interface m48t59: register a QOM type for each nvram type we support m48t59: move ISA ports/memory regions registration to QOM constructor Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
4ba4df405c
@ -159,6 +159,7 @@ F: hw/sh4/
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SPARC
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M: Blue Swirl <blauwirbel@gmail.com>
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M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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S: Maintained
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F: target-sparc/
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F: hw/sparc/
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@ -518,11 +519,13 @@ SPARC Machines
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--------------
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Sun4m
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M: Blue Swirl <blauwirbel@gmail.com>
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M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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S: Maintained
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F: hw/sparc/sun4m.c
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Sun4u
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M: Blue Swirl <blauwirbel@gmail.com>
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M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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S: Maintained
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F: hw/sparc64/sun4u.c
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161
hw/ppc/ppc.c
161
hw/ppc/ppc.c
@ -1318,167 +1318,6 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
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}
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}
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/*****************************************************************************/
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/* NVRAM helpers */
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static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
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{
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return (*nvram->read_fn)(nvram->opaque, addr);
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}
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static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
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{
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(*nvram->write_fn)(nvram->opaque, addr, val);
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}
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static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value)
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{
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nvram_write(nvram, addr, value);
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}
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static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr)
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{
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return nvram_read(nvram, addr);
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}
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static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value)
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{
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nvram_write(nvram, addr, value >> 8);
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nvram_write(nvram, addr + 1, value & 0xFF);
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}
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static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr)
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{
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uint16_t tmp;
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tmp = nvram_read(nvram, addr) << 8;
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tmp |= nvram_read(nvram, addr + 1);
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return tmp;
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}
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static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value)
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{
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nvram_write(nvram, addr, value >> 24);
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nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
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nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
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nvram_write(nvram, addr + 3, value & 0xFF);
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}
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uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
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{
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uint32_t tmp;
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tmp = nvram_read(nvram, addr) << 24;
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tmp |= nvram_read(nvram, addr + 1) << 16;
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tmp |= nvram_read(nvram, addr + 2) << 8;
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tmp |= nvram_read(nvram, addr + 3);
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return tmp;
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}
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static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str,
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uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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nvram_write(nvram, addr + i, str[i]);
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}
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nvram_write(nvram, addr + i, str[i]);
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nvram_write(nvram, addr + max - 1, '\0');
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}
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int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
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{
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int i;
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memset(dst, 0, max);
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for (i = 0; i < max; i++) {
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dst[i] = NVRAM_get_byte(nvram, addr + i);
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if (dst[i] == '\0')
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break;
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}
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return i;
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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#define CMDLINE_ADDR 0x017ff000
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int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
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const char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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if (cmdline) {
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/* XXX: put the cmdline in NVRAM too ? */
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pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
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NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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} else {
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NVRAM_set_lword(nvram, 0x40, 0);
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NVRAM_set_lword(nvram, 0x44, 0);
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}
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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NVRAM_set_word(nvram, 0x54, width);
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NVRAM_set_word(nvram, 0x56, height);
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NVRAM_set_word(nvram, 0x58, depth);
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crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
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NVRAM_set_word(nvram, 0xFC, crc);
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return 0;
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}
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/* CPU device-tree ID helpers */
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int ppc_get_vcpu_dt_id(PowerPCCPU *cpu)
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{
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@ -283,7 +283,7 @@ static void ref405ep_init(MachineState *machine)
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register NVRAM\n", __func__);
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#endif
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m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
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m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
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/* Load kernel */
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linux_boot = (kernel_filename != NULL);
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if (linux_boot) {
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163
hw/ppc/prep.c
163
hw/ppc/prep.c
@ -181,7 +181,7 @@ static const MemoryRegionOps PPC_XCSR_ops = {
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t {
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qemu_irq reset_irq;
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M48t59State *nvram;
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Nvram *nvram;
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uint8_t state;
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uint8_t syscontrol;
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int contiguous_map;
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@ -235,13 +235,17 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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break;
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case 0x0810:
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 1);
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 1);
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}
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break;
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case 0x0812:
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 2);
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 2);
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}
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break;
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case 0x0814:
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/* L2 invalidate register */
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@ -360,6 +364,144 @@ static const MemoryRegionPortio prep_portio_list[] = {
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static PortioList prep_port_list;
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/*****************************************************************************/
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/* NVRAM helpers */
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static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
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{
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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return (k->read)(nvram, addr);
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}
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static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
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{
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->write)(nvram, addr, val);
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}
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static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
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{
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nvram_write(nvram, addr, value);
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}
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static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
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{
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return nvram_read(nvram, addr);
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}
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static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
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{
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nvram_write(nvram, addr, value >> 8);
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nvram_write(nvram, addr + 1, value & 0xFF);
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}
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static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
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{
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uint16_t tmp;
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tmp = nvram_read(nvram, addr) << 8;
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tmp |= nvram_read(nvram, addr + 1);
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return tmp;
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}
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static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
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{
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nvram_write(nvram, addr, value >> 24);
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nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
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nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
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nvram_write(nvram, addr + 3, value & 0xFF);
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}
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static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
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uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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nvram_write(nvram, addr + i, str[i]);
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}
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nvram_write(nvram, addr + i, str[i]);
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nvram_write(nvram, addr + max - 1, '\0');
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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#define CMDLINE_ADDR 0x017ff000
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static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
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const char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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if (cmdline) {
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/* XXX: put the cmdline in NVRAM too ? */
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pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
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cmdline);
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NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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} else {
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NVRAM_set_lword(nvram, 0x40, 0);
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NVRAM_set_lword(nvram, 0x44, 0);
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}
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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NVRAM_set_word(nvram, 0x54, width);
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NVRAM_set_word(nvram, 0x56, height);
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NVRAM_set_word(nvram, 0x58, depth);
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crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
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NVRAM_set_word(nvram, 0xFC, crc);
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return 0;
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}
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/* PowerPC PREP hardware initialisation */
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static void ppc_prep_init(MachineState *machine)
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{
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@ -372,8 +514,7 @@ static void ppc_prep_init(MachineState *machine)
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MemoryRegion *sysmem = get_system_memory();
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PowerPCCPU *cpu = NULL;
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CPUPPCState *env = NULL;
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nvram_t nvram;
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M48t59State *m48t59;
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Nvram *m48t59;
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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#endif
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@ -543,16 +684,14 @@ static void ppc_prep_init(MachineState *machine)
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pci_create_simple(pci_bus, -1, "pci-ohci");
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}
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m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
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m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
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if (m48t59 == NULL)
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return;
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sysctrl->nvram = m48t59;
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||||
|
||||
/* Initialise NVRAM */
|
||||
nvram.opaque = m48t59;
|
||||
nvram.read_fn = &m48t59_read;
|
||||
nvram.write_fn = &m48t59_write;
|
||||
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
||||
PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
|
||||
ppc_boot_device,
|
||||
kernel_base, kernel_size,
|
||||
kernel_cmdline,
|
||||
initrd_base, initrd_size,
|
||||
|
||||
@ -127,7 +127,7 @@ static void fw_cfg_boot_set(void *opaque, const char *boot_device,
|
||||
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
||||
}
|
||||
|
||||
static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
|
||||
static void nvram_init(Nvram *nvram, uint8_t *macaddr,
|
||||
const char *cmdline, const char *boot_devices,
|
||||
ram_addr_t RAM_size, uint32_t kernel_size,
|
||||
int width, int height, int depth,
|
||||
@ -137,6 +137,7 @@ static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
|
||||
uint32_t start, end;
|
||||
uint8_t image[0x1ff0];
|
||||
struct OpenBIOS_nvpart_v1 *part_header;
|
||||
NvramClass *k = NVRAM_GET_CLASS(nvram);
|
||||
|
||||
memset(image, '\0', sizeof(image));
|
||||
|
||||
@ -170,8 +171,9 @@ static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
|
||||
Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
|
||||
nvram_machine_id);
|
||||
|
||||
for (i = 0; i < sizeof(image); i++)
|
||||
m48t59_write(nvram, i, image[i]);
|
||||
for (i = 0; i < sizeof(image); i++) {
|
||||
(k->write)(nvram, i, image[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static DeviceState *slavio_intctl;
|
||||
@ -1012,7 +1014,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
|
||||
|
||||
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
||||
|
||||
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
|
||||
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
|
||||
|
||||
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
||||
|
||||
|
||||
@ -130,7 +130,7 @@ static void fw_cfg_boot_set(void *opaque, const char *boot_device,
|
||||
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
||||
}
|
||||
|
||||
static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
|
||||
static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
|
||||
const char *arch, ram_addr_t RAM_size,
|
||||
const char *boot_devices,
|
||||
uint32_t kernel_image, uint32_t kernel_size,
|
||||
@ -144,6 +144,7 @@ static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
|
||||
uint32_t start, end;
|
||||
uint8_t image[0x1ff0];
|
||||
struct OpenBIOS_nvpart_v1 *part_header;
|
||||
NvramClass *k = NVRAM_GET_CLASS(nvram);
|
||||
|
||||
memset(image, '\0', sizeof(image));
|
||||
|
||||
@ -176,8 +177,9 @@ static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
|
||||
|
||||
Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
|
||||
|
||||
for (i = 0; i < sizeof(image); i++)
|
||||
m48t59_write(nvram, i, image[i]);
|
||||
for (i = 0; i < sizeof(image); i++) {
|
||||
(k->write)(nvram, i, image[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -610,7 +612,7 @@ pci_ebus_init1(PCIDevice *pci_dev)
|
||||
0, 0x1000000);
|
||||
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
|
||||
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
|
||||
0, 0x1000);
|
||||
0, 0x4000);
|
||||
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
|
||||
return 0;
|
||||
}
|
||||
@ -818,11 +820,12 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
|
||||
const struct hwdef *hwdef)
|
||||
{
|
||||
SPARCCPU *cpu;
|
||||
M48t59State *nvram;
|
||||
Nvram *nvram;
|
||||
unsigned int i;
|
||||
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
|
||||
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
|
||||
ISABus *isa_bus;
|
||||
SysBusDevice *s;
|
||||
qemu_irq *ivec_irqs, *pbm_irqs;
|
||||
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
|
||||
DriveInfo *fd[MAX_FD];
|
||||
@ -866,7 +869,12 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
|
||||
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
||||
}
|
||||
fdctrl_init_isa(isa_bus, fd);
|
||||
nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
|
||||
|
||||
/* Map NVRAM into I/O (ebus) space */
|
||||
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
|
||||
s = SYS_BUS_DEVICE(nvram);
|
||||
memory_region_add_subregion(get_system_io(), 0x2000,
|
||||
sysbus_mmio_get_region(s, 0));
|
||||
|
||||
initrd_size = 0;
|
||||
initrd_addr = 0;
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
|
||||
*
|
||||
* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
|
||||
* Copyright (c) 2013 Hervé Poussineau
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
@ -37,12 +38,35 @@
|
||||
#define NVRAM_PRINTF(fmt, ...) do { } while (0)
|
||||
#endif
|
||||
|
||||
#define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
|
||||
#define M48TXX_SYS_BUS_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
|
||||
#define M48TXX_SYS_BUS_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
|
||||
#define M48TXX_SYS_BUS(obj) \
|
||||
OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
|
||||
|
||||
#define TYPE_M48TXX_ISA "isa-m48txx"
|
||||
#define M48TXX_ISA_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
|
||||
#define M48TXX_ISA_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
|
||||
#define M48TXX_ISA(obj) \
|
||||
OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
|
||||
|
||||
/*
|
||||
* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
|
||||
* alarm and a watchdog timer and related control registers. In the
|
||||
* PPC platform there is also a nvram lock function.
|
||||
*/
|
||||
|
||||
typedef struct M48txxInfo {
|
||||
const char *isa_name;
|
||||
const char *sysbus_name;
|
||||
uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
|
||||
uint32_t size;
|
||||
} M48txxInfo;
|
||||
|
||||
/*
|
||||
* Chipset docs:
|
||||
* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
|
||||
@ -50,12 +74,12 @@
|
||||
* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
|
||||
*/
|
||||
|
||||
struct M48t59State {
|
||||
typedef struct M48t59State {
|
||||
/* Hardware parameters */
|
||||
qemu_irq IRQ;
|
||||
MemoryRegion iomem;
|
||||
uint32_t io_base;
|
||||
uint32_t size;
|
||||
int32_t base_year;
|
||||
/* RTC management */
|
||||
time_t time_offset;
|
||||
time_t stop_time;
|
||||
@ -70,28 +94,51 @@ struct M48t59State {
|
||||
/* NVRAM storage */
|
||||
uint16_t addr;
|
||||
uint8_t lock;
|
||||
} M48t59State;
|
||||
|
||||
typedef struct M48txxISAState {
|
||||
ISADevice parent_obj;
|
||||
M48t59State state;
|
||||
uint32_t io_base;
|
||||
MemoryRegion io;
|
||||
} M48txxISAState;
|
||||
|
||||
typedef struct M48txxISADeviceClass {
|
||||
ISADeviceClass parent_class;
|
||||
M48txxInfo info;
|
||||
} M48txxISADeviceClass;
|
||||
|
||||
typedef struct M48txxSysBusState {
|
||||
SysBusDevice parent_obj;
|
||||
M48t59State state;
|
||||
MemoryRegion io;
|
||||
} M48txxSysBusState;
|
||||
|
||||
typedef struct M48txxSysBusDeviceClass {
|
||||
SysBusDeviceClass parent_class;
|
||||
M48txxInfo info;
|
||||
} M48txxSysBusDeviceClass;
|
||||
|
||||
static M48txxInfo m48txx_info[] = {
|
||||
{
|
||||
.sysbus_name = "sysbus-m48t02",
|
||||
.model = 2,
|
||||
.size = 0x800,
|
||||
},{
|
||||
.sysbus_name = "sysbus-m48t08",
|
||||
.model = 8,
|
||||
.size = 0x2000,
|
||||
},{
|
||||
.sysbus_name = "sysbus-m48t59",
|
||||
.model = 59,
|
||||
.size = 0x2000,
|
||||
},{
|
||||
.isa_name = "isa-m48t59",
|
||||
.model = 59,
|
||||
.size = 0x2000,
|
||||
}
|
||||
};
|
||||
|
||||
#define TYPE_ISA_M48T59 "m48t59_isa"
|
||||
#define ISA_M48T59(obj) \
|
||||
OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59)
|
||||
|
||||
typedef struct M48t59ISAState {
|
||||
ISADevice parent_obj;
|
||||
|
||||
M48t59State state;
|
||||
MemoryRegion io;
|
||||
} M48t59ISAState;
|
||||
|
||||
#define SYSBUS_M48T59(obj) \
|
||||
OBJECT_CHECK(M48t59SysBusState, (obj), TYPE_SYSBUS_M48T59)
|
||||
|
||||
typedef struct M48t59SysBusState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
M48t59State state;
|
||||
MemoryRegion io;
|
||||
} M48t59SysBusState;
|
||||
|
||||
/* Fake timer functions */
|
||||
|
||||
@ -198,9 +245,8 @@ static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
|
||||
}
|
||||
|
||||
/* Direct access to NVRAM */
|
||||
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
|
||||
static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
|
||||
{
|
||||
M48t59State *NVRAM = opaque;
|
||||
struct tm tm;
|
||||
int tmp;
|
||||
|
||||
@ -346,11 +392,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
|
||||
tmp = from_bcd(val);
|
||||
if (tmp >= 0 && tmp <= 99) {
|
||||
get_time(NVRAM, &tm);
|
||||
if (NVRAM->model == 8) {
|
||||
tm.tm_year = from_bcd(val) + 68; // Base year is 1968
|
||||
} else {
|
||||
tm.tm_year = from_bcd(val);
|
||||
}
|
||||
tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
|
||||
set_time(NVRAM, &tm);
|
||||
}
|
||||
break;
|
||||
@ -368,9 +410,8 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t m48t59_read (void *opaque, uint32_t addr)
|
||||
static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
|
||||
{
|
||||
M48t59State *NVRAM = opaque;
|
||||
struct tm tm;
|
||||
uint32_t retval = 0xFF;
|
||||
|
||||
@ -453,11 +494,7 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
|
||||
case 0x07FF:
|
||||
/* year */
|
||||
get_time(NVRAM, &tm);
|
||||
if (NVRAM->model == 8) {
|
||||
retval = to_bcd(tm.tm_year - 68); // Base year is 1968
|
||||
} else {
|
||||
retval = to_bcd(tm.tm_year);
|
||||
}
|
||||
retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
|
||||
break;
|
||||
default:
|
||||
/* Check lock registers state */
|
||||
@ -477,10 +514,8 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
|
||||
return retval;
|
||||
}
|
||||
|
||||
void m48t59_toggle_lock (void *opaque, int lock)
|
||||
static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
|
||||
{
|
||||
M48t59State *NVRAM = opaque;
|
||||
|
||||
NVRAM->lock ^= 1 << lock;
|
||||
}
|
||||
|
||||
@ -616,7 +651,7 @@ static void m48t59_reset_common(M48t59State *NVRAM)
|
||||
|
||||
static void m48t59_reset_isa(DeviceState *d)
|
||||
{
|
||||
M48t59ISAState *isa = ISA_M48T59(d);
|
||||
M48txxISAState *isa = M48TXX_ISA(d);
|
||||
M48t59State *NVRAM = &isa->state;
|
||||
|
||||
m48t59_reset_common(NVRAM);
|
||||
@ -624,7 +659,7 @@ static void m48t59_reset_isa(DeviceState *d)
|
||||
|
||||
static void m48t59_reset_sysbus(DeviceState *d)
|
||||
{
|
||||
M48t59SysBusState *sys = SYSBUS_M48T59(d);
|
||||
M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
|
||||
M48t59State *NVRAM = &sys->state;
|
||||
|
||||
m48t59_reset_common(NVRAM);
|
||||
@ -641,58 +676,63 @@ static const MemoryRegionOps m48t59_io_ops = {
|
||||
};
|
||||
|
||||
/* Initialisation routine */
|
||||
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int model)
|
||||
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int base_year,
|
||||
int model)
|
||||
{
|
||||
DeviceState *dev;
|
||||
SysBusDevice *s;
|
||||
M48t59SysBusState *d;
|
||||
M48t59State *state;
|
||||
int i;
|
||||
|
||||
dev = qdev_create(NULL, TYPE_SYSBUS_M48T59);
|
||||
qdev_prop_set_uint32(dev, "model", model);
|
||||
qdev_prop_set_uint32(dev, "size", size);
|
||||
qdev_prop_set_uint32(dev, "io_base", io_base);
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
|
||||
if (!m48txx_info[i].sysbus_name ||
|
||||
m48txx_info[i].size != size ||
|
||||
m48txx_info[i].model != model) {
|
||||
continue;
|
||||
}
|
||||
|
||||
dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
|
||||
qdev_prop_set_int32(dev, "base-year", base_year);
|
||||
qdev_init_nofail(dev);
|
||||
s = SYS_BUS_DEVICE(dev);
|
||||
d = SYSBUS_M48T59(dev);
|
||||
state = &d->state;
|
||||
sysbus_connect_irq(s, 0, IRQ);
|
||||
memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, state,
|
||||
"m48t59", 4);
|
||||
if (io_base != 0) {
|
||||
memory_region_add_subregion(get_system_io(), io_base, &d->io);
|
||||
memory_region_add_subregion(get_system_io(), io_base,
|
||||
sysbus_mmio_get_region(s, 1));
|
||||
}
|
||||
if (mem_base != 0) {
|
||||
sysbus_mmio_map(s, 0, mem_base);
|
||||
}
|
||||
|
||||
return state;
|
||||
return NVRAM(s);
|
||||
}
|
||||
|
||||
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int model)
|
||||
assert(false);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int base_year, int model)
|
||||
{
|
||||
M48t59ISAState *d;
|
||||
ISADevice *isadev;
|
||||
DeviceState *dev;
|
||||
M48t59State *s;
|
||||
int i;
|
||||
|
||||
isadev = isa_create(bus, TYPE_ISA_M48T59);
|
||||
dev = DEVICE(isadev);
|
||||
qdev_prop_set_uint32(dev, "model", model);
|
||||
qdev_prop_set_uint32(dev, "size", size);
|
||||
qdev_prop_set_uint32(dev, "io_base", io_base);
|
||||
qdev_init_nofail(dev);
|
||||
d = ISA_M48T59(isadev);
|
||||
s = &d->state;
|
||||
|
||||
memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, s, "m48t59", 4);
|
||||
if (io_base != 0) {
|
||||
isa_register_ioport(isadev, &d->io, io_base);
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
|
||||
if (!m48txx_info[i].isa_name ||
|
||||
m48txx_info[i].size != size ||
|
||||
m48txx_info[i].model != model) {
|
||||
continue;
|
||||
}
|
||||
|
||||
return s;
|
||||
dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
|
||||
qdev_prop_set_uint32(dev, "iobase", io_base);
|
||||
qdev_prop_set_int32(dev, "base-year", base_year);
|
||||
qdev_init_nofail(dev);
|
||||
return NVRAM(dev);
|
||||
}
|
||||
|
||||
assert(false);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void m48t59_realize_common(M48t59State *s, Error **errp)
|
||||
@ -709,25 +749,38 @@ static void m48t59_realize_common(M48t59State *s, Error **errp)
|
||||
|
||||
static void m48t59_isa_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
|
||||
ISADevice *isadev = ISA_DEVICE(dev);
|
||||
M48t59ISAState *d = ISA_M48T59(dev);
|
||||
M48txxISAState *d = M48TXX_ISA(dev);
|
||||
M48t59State *s = &d->state;
|
||||
|
||||
s->model = u->info.model;
|
||||
s->size = u->info.size;
|
||||
isa_init_irq(isadev, &s->IRQ, 8);
|
||||
m48t59_realize_common(s, errp);
|
||||
memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
|
||||
if (d->io_base != 0) {
|
||||
isa_register_ioport(isadev, &d->io, d->io_base);
|
||||
}
|
||||
}
|
||||
|
||||
static int m48t59_init1(SysBusDevice *dev)
|
||||
{
|
||||
M48t59SysBusState *d = SYSBUS_M48T59(dev);
|
||||
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
|
||||
M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
|
||||
Object *o = OBJECT(dev);
|
||||
M48t59State *s = &d->state;
|
||||
Error *err = NULL;
|
||||
|
||||
s->model = u->info.model;
|
||||
s->size = u->info.size;
|
||||
sysbus_init_irq(dev, &s->IRQ);
|
||||
|
||||
memory_region_init_io(&s->iomem, OBJECT(d), &nvram_ops, s,
|
||||
"m48t59.nvram", s->size);
|
||||
memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
|
||||
s->size);
|
||||
memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_mmio(dev, &d->io);
|
||||
m48t59_realize_common(s, &err);
|
||||
if (err != NULL) {
|
||||
error_free(err);
|
||||
@ -737,59 +790,157 @@ static int m48t59_init1(SysBusDevice *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
return m48t59_read(&d->state, addr);
|
||||
}
|
||||
|
||||
static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
m48t59_write(&d->state, addr, val);
|
||||
}
|
||||
|
||||
static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
m48t59_toggle_lock(&d->state, lock);
|
||||
}
|
||||
|
||||
static Property m48t59_isa_properties[] = {
|
||||
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
|
||||
DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1),
|
||||
DEFINE_PROP_UINT32("io_base", M48t59ISAState, state.io_base, 0),
|
||||
DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
|
||||
DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void m48t59_isa_class_init(ObjectClass *klass, void *data)
|
||||
static void m48txx_isa_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
NvramClass *nc = NVRAM_CLASS(klass);
|
||||
|
||||
dc->realize = m48t59_isa_realize;
|
||||
dc->reset = m48t59_reset_isa;
|
||||
dc->props = m48t59_isa_properties;
|
||||
/* Reason: needs to be wired up by m48t59_init_isa() */
|
||||
dc->cannot_instantiate_with_device_add_yet = true;
|
||||
nc->read = m48txx_isa_read;
|
||||
nc->write = m48txx_isa_write;
|
||||
nc->toggle_lock = m48txx_isa_toggle_lock;
|
||||
}
|
||||
|
||||
static const TypeInfo m48t59_isa_info = {
|
||||
.name = TYPE_ISA_M48T59,
|
||||
.parent = TYPE_ISA_DEVICE,
|
||||
.instance_size = sizeof(M48t59ISAState),
|
||||
.class_init = m48t59_isa_class_init,
|
||||
};
|
||||
static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
|
||||
M48txxInfo *info = data;
|
||||
|
||||
static Property m48t59_properties[] = {
|
||||
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
|
||||
DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1),
|
||||
DEFINE_PROP_UINT32("io_base", M48t59SysBusState, state.io_base, 0),
|
||||
u->info = *info;
|
||||
}
|
||||
|
||||
static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
|
||||
{
|
||||
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
||||
return m48t59_read(&d->state, addr);
|
||||
}
|
||||
|
||||
static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
|
||||
{
|
||||
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
||||
m48t59_write(&d->state, addr, val);
|
||||
}
|
||||
|
||||
static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
|
||||
{
|
||||
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
||||
m48t59_toggle_lock(&d->state, lock);
|
||||
}
|
||||
|
||||
static Property m48t59_sysbus_properties[] = {
|
||||
DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void m48t59_class_init(ObjectClass *klass, void *data)
|
||||
static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||||
NvramClass *nc = NVRAM_CLASS(klass);
|
||||
|
||||
k->init = m48t59_init1;
|
||||
dc->reset = m48t59_reset_sysbus;
|
||||
dc->props = m48t59_properties;
|
||||
dc->props = m48t59_sysbus_properties;
|
||||
nc->read = m48txx_sysbus_read;
|
||||
nc->write = m48txx_sysbus_write;
|
||||
nc->toggle_lock = m48txx_sysbus_toggle_lock;
|
||||
}
|
||||
|
||||
static const TypeInfo m48t59_info = {
|
||||
.name = TYPE_SYSBUS_M48T59,
|
||||
static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
|
||||
M48txxInfo *info = data;
|
||||
|
||||
u->info = *info;
|
||||
}
|
||||
|
||||
static const TypeInfo nvram_info = {
|
||||
.name = TYPE_NVRAM,
|
||||
.parent = TYPE_INTERFACE,
|
||||
.class_size = sizeof(NvramClass),
|
||||
};
|
||||
|
||||
static const TypeInfo m48txx_sysbus_type_info = {
|
||||
.name = TYPE_M48TXX_SYS_BUS,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(M48t59SysBusState),
|
||||
.class_init = m48t59_class_init,
|
||||
.instance_size = sizeof(M48txxSysBusState),
|
||||
.abstract = true,
|
||||
.class_init = m48txx_sysbus_class_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ TYPE_NVRAM },
|
||||
{ }
|
||||
}
|
||||
};
|
||||
|
||||
static const TypeInfo m48txx_isa_type_info = {
|
||||
.name = TYPE_M48TXX_ISA,
|
||||
.parent = TYPE_ISA_DEVICE,
|
||||
.instance_size = sizeof(M48txxISAState),
|
||||
.abstract = true,
|
||||
.class_init = m48txx_isa_class_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ TYPE_NVRAM },
|
||||
{ }
|
||||
}
|
||||
};
|
||||
|
||||
static void m48t59_register_types(void)
|
||||
{
|
||||
type_register_static(&m48t59_info);
|
||||
type_register_static(&m48t59_isa_info);
|
||||
TypeInfo sysbus_type_info = {
|
||||
.parent = TYPE_M48TXX_SYS_BUS,
|
||||
.class_size = sizeof(M48txxSysBusDeviceClass),
|
||||
.class_init = m48txx_sysbus_concrete_class_init,
|
||||
};
|
||||
TypeInfo isa_type_info = {
|
||||
.parent = TYPE_M48TXX_ISA,
|
||||
.class_size = sizeof(M48txxISADeviceClass),
|
||||
.class_init = m48txx_isa_concrete_class_init,
|
||||
};
|
||||
int i;
|
||||
|
||||
type_register_static(&nvram_info);
|
||||
type_register_static(&m48txx_sysbus_type_info);
|
||||
type_register_static(&m48txx_isa_type_info);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
|
||||
if (m48txx_info[i].sysbus_name) {
|
||||
sysbus_type_info.name = m48txx_info[i].sysbus_name;
|
||||
sysbus_type_info.class_data = &m48txx_info[i];
|
||||
type_register(&sysbus_type_info);
|
||||
}
|
||||
|
||||
if (m48txx_info[i].isa_name) {
|
||||
isa_type_info.name = m48txx_info[i].isa_name;
|
||||
isa_type_info.class_data = &m48txx_info[i];
|
||||
type_register(&isa_type_info);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
type_init(m48t59_register_types)
|
||||
|
||||
@ -1,37 +1,34 @@
|
||||
#ifndef NVRAM_H
|
||||
#define NVRAM_H
|
||||
|
||||
/* NVRAM helpers */
|
||||
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
|
||||
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
|
||||
typedef struct nvram_t {
|
||||
void *opaque;
|
||||
nvram_read_t read_fn;
|
||||
nvram_write_t write_fn;
|
||||
} nvram_t;
|
||||
#include "qemu-common.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
|
||||
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
|
||||
#define TYPE_NVRAM "nvram"
|
||||
|
||||
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
||||
const char *arch,
|
||||
uint32_t RAM_size, int boot_device,
|
||||
uint32_t kernel_image, uint32_t kernel_size,
|
||||
const char *cmdline,
|
||||
uint32_t initrd_image, uint32_t initrd_size,
|
||||
uint32_t NVRAM_image,
|
||||
int width, int height, int depth);
|
||||
#define NVRAM_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(NvramClass, (klass), TYPE_NVRAM)
|
||||
#define NVRAM_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(NvramClass, (obj), TYPE_NVRAM)
|
||||
#define NVRAM(obj) \
|
||||
INTERFACE_CHECK(Nvram, (obj), TYPE_NVRAM)
|
||||
|
||||
#define TYPE_SYSBUS_M48T59 "m48t59"
|
||||
typedef struct Nvram {
|
||||
Object parent;
|
||||
} Nvram;
|
||||
|
||||
typedef struct M48t59State M48t59State;
|
||||
typedef struct NvramClass {
|
||||
InterfaceClass parent;
|
||||
|
||||
void m48t59_write (void *private, uint32_t addr, uint32_t val);
|
||||
uint32_t m48t59_read (void *private, uint32_t addr);
|
||||
void m48t59_toggle_lock (void *private, int lock);
|
||||
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
uint32_t (*read)(Nvram *obj, uint32_t addr);
|
||||
void (*write)(Nvram *obj, uint32_t addr, uint32_t val);
|
||||
void (*toggle_lock)(Nvram *obj, int lock);
|
||||
} NvramClass;
|
||||
|
||||
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int base_year, int type);
|
||||
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int base_year,
|
||||
int type);
|
||||
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int type);
|
||||
|
||||
#endif /* !NVRAM_H */
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -2052,7 +2052,7 @@ firmware implementation. The goal is to implement a 100% IEEE
|
||||
|
||||
A sample Linux 2.6 series kernel and ram disk image are available on
|
||||
the QEMU web site. There are still issues with NetBSD and OpenBSD, but
|
||||
some kernel versions work. Please note that currently older Solaris kernels
|
||||
most kernel versions work. Please note that currently older Solaris kernels
|
||||
don't work probably due to interface issues between OpenBIOS and
|
||||
Solaris.
|
||||
|
||||
@ -2091,8 +2091,9 @@ Set the emulated machine type. Default is SS-5.
|
||||
|
||||
Use the executable @file{qemu-system-sparc64} to simulate a Sun4u
|
||||
(UltraSPARC PC-like machine), Sun4v (T1 PC-like machine), or generic
|
||||
Niagara (T1) machine. The emulator is not usable for anything yet, but
|
||||
it can launch some kernels.
|
||||
Niagara (T1) machine. The Sun4u emulator is mostly complete, being
|
||||
able to run Linux, NetBSD and OpenBSD in headless (-nographic) mode. The
|
||||
Sun4v and Niagara emulators are still a work in progress.
|
||||
|
||||
QEMU emulates the following peripherals:
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Subproject commit 038aa78d3c331731733378a73e778ee620a5b9da
|
||||
Subproject commit b8dea39718916f4d7d391cd1664314d52a45b872
|
||||
Loading…
Reference in New Issue
Block a user