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The DTrace via SystemTap backend can not support the dynamic '*' width

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format. We failed at noticing it for the 4.1 release, and LP#1844817
 was opened to track it. Fix this regression for the next release.
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Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20191119' into staging

The DTrace via SystemTap backend can not support the dynamic '*' width
format. We failed at noticing it for the 4.1 release, and LP#1844817
was opened to track it. Fix this regression for the next release.

# gpg: Signature made Tue 19 Nov 2019 13:56:50 GMT
# gpg:                using RSA key 89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (Phil) <philmd@redhat.com>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 89C1 E78F 601E E86C 8674  95CB A2A3 FD6E DEAD C0DE

* remotes/philmd-gitlab/tags/mips-next-20191119:
  hw/mips/gt64xxx: Remove dynamic field width from trace events
  hw/block/pflash: Remove dynamic field width from trace events

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-11-19 15:55:33 +00:00
commit 4b8be65ec5
5 changed files with 22 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/block/pflash_cfi01.c
View File

@ -276,7 +276,7 @@ static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset,
DPRINTF("BUG in %s\n", __func__);
abort();
}
trace_pflash_data_read(offset, width << 1, ret);
trace_pflash_data_read(offset, width, ret);
return ret;
}
@ -389,7 +389,7 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
break;
}
trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle);
return ret;
}
@ -414,7 +414,7 @@ static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset,
{
uint8_t *p = pfl->storage;
trace_pflash_data_write(offset, width << 1, value, pfl->counter);
trace_pflash_data_write(offset, width, value, pfl->counter);
switch (width) {
case 1:
p[offset] = value;
@ -453,7 +453,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
cmd = value;
trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
trace_pflash_io_write(offset, width, value, pfl->wcycle);
if (!pfl->wcycle) {
/* Set the device in I/O access mode */
memory_region_rom_device_set_romd(&pfl->mem, false);

8
hw/block/pflash_cfi02.c
View File

@ -260,7 +260,7 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
{
uint8_t *p = (uint8_t *)pfl->storage + offset;
uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
trace_pflash_data_read(offset, width << 1, ret);
trace_pflash_data_read(offset, width, ret);
return ret;
}
@ -385,7 +385,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
}
break;
}
trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle);
return ret;
}
@ -432,7 +432,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
uint8_t *p;
uint8_t cmd;
trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
trace_pflash_io_write(offset, width, value, pfl->wcycle);
cmd = value;
if (pfl->cmd != 0xA0) {
/* Reset does nothing during chip erase and sector erase. */
@ -542,7 +542,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
}
goto reset_flash;
}
trace_pflash_data_write(offset, width << 1, value, 0);
trace_pflash_data_write(offset, width, value, 0);
if (!pfl->ro) {
p = (uint8_t *)pfl->storage + offset;
if (pfl->be) {

8
hw/block/trace-events
View File

@ -8,10 +8,10 @@ fdc_ioport_write(uint8_t reg, uint8_t value) "write reg 0x%02x val 0x%02x"
# pflash_cfi01.c
pflash_reset(void) "reset"
pflash_timer_expired(uint8_t cmd) "command 0x%02x done"
pflash_io_read(uint64_t offset, int width, int fmt_width, uint32_t value, uint8_t cmd, uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x cmd:0x%02x wcycle:%u"
pflash_io_write(uint64_t offset, int width, int fmt_width, uint32_t value, uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x wcycle:%u"
pflash_data_read(uint64_t offset, int width, uint32_t value) "data offset:0x%04"PRIx64" value:0x%0*x"
pflash_data_write(uint64_t offset, int width, uint32_t value, uint64_t counter) "data offset:0x%04"PRIx64" value:0x%0*x counter:0x%016"PRIx64
pflash_io_read(uint64_t offset, unsigned size, uint32_t value, uint8_t cmd, uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x cmd:0x%02x wcycle:%u"
pflash_io_write(uint64_t offset, unsigned size, uint32_t value, uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x wcycle:%u"
pflash_data_read(uint64_t offset, unsigned size, uint32_t value) "data offset:0x%04"PRIx64" size:%u value:0x%04x"
pflash_data_write(uint64_t offset, unsigned size, uint32_t value, uint64_t counter) "data offset:0x%04"PRIx64" size:%u value:0x%04x counter:0x%016"PRIx64
pflash_manufacturer_id(uint16_t id) "Read Manufacturer ID: 0x%04x"
pflash_device_id(uint16_t id) "Read Device ID: 0x%04x"
pflash_device_info(uint64_t offset) "Read Device Information offset:0x%04"PRIx64

16
hw/mips/gt64xxx_pci.c
View File

@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* not really implemented */
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
trace_gt64120_write("INTRCAUSE", size << 1, val);
trace_gt64120_write("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
s->regs[saddr] = val & 0x3c3ffffe;
trace_gt64120_write("INTRMASK", size << 1, val);
trace_gt64120_write("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
s->regs[saddr] = val & 0x03fffffe;
trace_gt64120_write("ICMASK", size << 1, val);
trace_gt64120_write("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
s->regs[saddr] = val & 0x0000003f;
trace_gt64120_write("SERR0MASK", size << 1, val);
trace_gt64120_write("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque,
/* Interrupts */
case GT_INTRCAUSE:
val = s->regs[saddr];
trace_gt64120_read("INTRCAUSE", size << 1, val);
trace_gt64120_read("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
val = s->regs[saddr];
trace_gt64120_read("INTRMASK", size << 1, val);
trace_gt64120_read("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
val = s->regs[saddr];
trace_gt64120_read("ICMASK", size << 1, val);
trace_gt64120_read("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
val = s->regs[saddr];
trace_gt64120_read("SERR0MASK", size << 1, val);
trace_gt64120_read("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */

4
hw/mips/trace-events
View File

@ -1,4 +1,4 @@
# gt64xxx.c
gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64
gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64
gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64