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omap1: convert to memory API (part I)

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Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-08-09 19:35:00 +03:00
parent 19b4a424d8
commit 4b3fedf3a5
4 changed files with 203 additions and 154 deletions
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11
hw/omap.h
View File

@ -826,6 +826,14 @@ struct omap_mpu_state_s {
qemu_irq wakeup; qemu_irq wakeup;
MemoryRegion ulpd_pm_iomem;
MemoryRegion pin_cfg_iomem;
MemoryRegion id_iomem;
MemoryRegion id_iomem_e18;
MemoryRegion id_iomem_ed4;
MemoryRegion id_iomem_e20;
MemoryRegion mpui_iomem;
struct omap_dma_port_if_s { struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s, uint32_t (*read[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset); target_phys_addr_t offset);
@ -947,7 +955,8 @@ struct omap_mpu_state_s {
}; };
/* omap1.c */ /* omap1.c */
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
unsigned long sdram_size,
const char *core); const char *core);
/* omap2.c */ /* omap2.c */

338
hw/omap1.c
View File

@ -84,6 +84,7 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
/* MPU OS timers */ /* MPU OS timers */
struct omap_mpu_timer_s { struct omap_mpu_timer_s {
MemoryRegion iomem;
qemu_irq irq; qemu_irq irq;
omap_clk clk; omap_clk clk;
uint32_t val; uint32_t val;
@ -179,10 +180,15 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
timer->rate = omap_clk_getrate(timer->clk); timer->rate = omap_clk_getrate(timer->clk);
} }
static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) { switch (addr) {
case 0x00: /* CNTL_TIMER */ case 0x00: /* CNTL_TIMER */
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
@ -199,10 +205,14 @@ static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) { switch (addr) {
case 0x00: /* CNTL_TIMER */ case 0x00: /* CNTL_TIMER */
omap_timer_sync(s); omap_timer_sync(s);
@ -226,16 +236,10 @@ static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = { static const MemoryRegionOps omap_mpu_timer_ops = {
omap_badwidth_read32, .read = omap_mpu_timer_read,
omap_badwidth_read32, .write = omap_mpu_timer_write,
omap_mpu_timer_read, .endianness = DEVICE_LITTLE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_mpu_timer_write,
}; };
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
@ -250,10 +254,10 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
s->it_ena = 1; s->it_ena = 1;
} }
static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
target_phys_addr_t base,
qemu_irq irq, omap_clk clk) qemu_irq irq, omap_clk clk)
{ {
int iomemtype;
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
g_malloc0(sizeof(struct omap_mpu_timer_s)); g_malloc0(sizeof(struct omap_mpu_timer_s));
@ -264,9 +268,10 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
omap_mpu_timer_reset(s); omap_mpu_timer_reset(s);
omap_timer_clk_setup(s); omap_timer_clk_setup(s);
iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn, memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN); "omap-mpu-timer", 0x100);
cpu_register_physical_memory(base, 0x100, iomemtype);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s; return s;
} }
@ -274,16 +279,22 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
/* Watchdog timer */ /* Watchdog timer */
struct omap_watchdog_timer_s { struct omap_watchdog_timer_s {
struct omap_mpu_timer_s timer; struct omap_mpu_timer_s timer;
MemoryRegion iomem;
uint8_t last_wr; uint8_t last_wr;
int mode; int mode;
int free; int free;
int reset; int reset;
}; };
static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) { switch (addr) {
case 0x00: /* CNTL_TIMER */ case 0x00: /* CNTL_TIMER */
return (s->timer.ptv << 9) | (s->timer.ar << 8) | return (s->timer.ptv << 9) | (s->timer.ar << 8) |
@ -301,10 +312,14 @@ static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) { switch (addr) {
case 0x00: /* CNTL_TIMER */ case 0x00: /* CNTL_TIMER */
omap_timer_sync(&s->timer); omap_timer_sync(&s->timer);
@ -344,16 +359,10 @@ static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = { static const MemoryRegionOps omap_wd_timer_ops = {
omap_badwidth_read16, .read = omap_wd_timer_read,
omap_wd_timer_read, .write = omap_wd_timer_write,
omap_badwidth_read16, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {
omap_badwidth_write16,
omap_wd_timer_write,
omap_badwidth_write16,
}; };
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
@ -374,10 +383,10 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
omap_timer_update(&s->timer); omap_timer_update(&s->timer);
} }
static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
target_phys_addr_t base,
qemu_irq irq, omap_clk clk) qemu_irq irq, omap_clk clk)
{ {
int iomemtype;
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
g_malloc0(sizeof(struct omap_watchdog_timer_s)); g_malloc0(sizeof(struct omap_watchdog_timer_s));
@ -387,9 +396,9 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
omap_wd_timer_reset(s); omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer); omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(omap_wd_timer_readfn, memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN); "omap-wd-timer", 0x100);
cpu_register_physical_memory(base, 0x100, iomemtype); memory_region_add_subregion(memory, base, &s->iomem);
return s; return s;
} }
@ -397,13 +406,19 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
/* 32-kHz timer */ /* 32-kHz timer */
struct omap_32khz_timer_s { struct omap_32khz_timer_s {
struct omap_mpu_timer_s timer; struct omap_mpu_timer_s timer;
MemoryRegion iomem;
}; };
static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK; int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (offset) { switch (offset) {
case 0x00: /* TVR */ case 0x00: /* TVR */
return s->timer.reset_val; return s->timer.reset_val;
@ -422,11 +437,15 @@ static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK; int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (offset) { switch (offset) {
case 0x00: /* TVR */ case 0x00: /* TVR */
s->timer.reset_val = value & 0x00ffffff; s->timer.reset_val = value & 0x00ffffff;
@ -452,16 +471,10 @@ static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_os_timer_readfn[] = { static const MemoryRegionOps omap_os_timer_ops = {
omap_badwidth_read32, .read = omap_os_timer_read,
omap_badwidth_read32, .write = omap_os_timer_write,
omap_os_timer_read, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_os_timer_write,
}; };
static void omap_os_timer_reset(struct omap_32khz_timer_s *s) static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
@ -476,10 +489,10 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
s->timer.ar = 1; s->timer.ar = 1;
} }
static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
target_phys_addr_t base,
qemu_irq irq, omap_clk clk) qemu_irq irq, omap_clk clk)
{ {
int iomemtype;
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
g_malloc0(sizeof(struct omap_32khz_timer_s)); g_malloc0(sizeof(struct omap_32khz_timer_s));
@ -489,19 +502,24 @@ static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
omap_os_timer_reset(s); omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer); omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(omap_os_timer_readfn, memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN); "omap-os-timer", 0x800);
cpu_register_physical_memory(base, 0x800, iomemtype); memory_region_add_subregion(memory, base, &s->iomem);
return s; return s;
} }
/* Ultra Low-Power Device Module */ /* Ultra Low-Power Device Module */
static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t ret; uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) { switch (addr) {
case 0x14: /* IT_STATUS */ case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2]; ret = s->ulpd_pm_regs[addr >> 2];
@ -560,7 +578,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
} }
static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int64_t now, ticks; int64_t now, ticks;
@ -568,6 +586,10 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
static const int bypass_div[4] = { 1, 2, 4, 4 }; static const int bypass_div[4] = { 1, 2, 4, 4 };
uint16_t diff; uint16_t diff;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) { switch (addr) {
case 0x00: /* COUNTER_32_LSB */ case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */ case 0x04: /* COUNTER_32_MSB */
@ -674,16 +696,10 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = { static const MemoryRegionOps omap_ulpd_pm_ops = {
omap_badwidth_read16, .read = omap_ulpd_pm_read,
omap_ulpd_pm_read, .write = omap_ulpd_pm_write,
omap_badwidth_read16, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {
omap_badwidth_write16,
omap_ulpd_pm_write,
omap_badwidth_write16,
}; };
static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
@ -713,21 +729,26 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
} }
static void omap_ulpd_pm_init(target_phys_addr_t base, static void omap_ulpd_pm_init(MemoryRegion *system_memory,
target_phys_addr_t base,
struct omap_mpu_state_s *mpu) struct omap_mpu_state_s *mpu)
{ {
int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn, memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN); "omap-ulpd-pm", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_ulpd_pm_reset(mpu); omap_ulpd_pm_reset(mpu);
} }
/* OMAP Pin Configuration */ /* OMAP Pin Configuration */
static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) { switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */ case 0x00: /* FUNC_MUX_CTRL_0 */
case 0x04: /* FUNC_MUX_CTRL_1 */ case 0x04: /* FUNC_MUX_CTRL_1 */
@ -827,11 +848,15 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
} }
static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t diff; uint32_t diff;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) { switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */ case 0x00: /* FUNC_MUX_CTRL_0 */
diff = s->func_mux_ctrl[addr >> 2] ^ value; diff = s->func_mux_ctrl[addr >> 2] ^ value;
@ -900,16 +925,10 @@ static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = { static const MemoryRegionOps omap_pin_cfg_ops = {
omap_badwidth_read32, .read = omap_pin_cfg_read,
omap_badwidth_read32, .write = omap_pin_cfg_write,
omap_pin_cfg_read, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_pin_cfg_write,
}; };
static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
@ -928,21 +947,26 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
} }
static void omap_pin_cfg_init(target_phys_addr_t base, static void omap_pin_cfg_init(MemoryRegion *system_memory,
target_phys_addr_t base,
struct omap_mpu_state_s *mpu) struct omap_mpu_state_s *mpu)
{ {
int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn, memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN); "omap-pin-cfg", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_pin_cfg_reset(mpu); omap_pin_cfg_reset(mpu);
} }
/* Device Identification, Die Identification */ /* Device Identification, Die Identification */
static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) { switch (addr) {
case 0xfffe1800: /* DIE_ID_LSB */ case 0xfffe1800: /* DIE_ID_LSB */
return 0xc9581f0e; return 0xc9581f0e;
@ -982,38 +1006,48 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_id_write(void *opaque, target_phys_addr_t addr, static void omap_id_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
OMAP_BAD_REG(addr); OMAP_BAD_REG(addr);
} }
static CPUReadMemoryFunc * const omap_id_readfn[] = { static const MemoryRegionOps omap_id_ops = {
omap_badwidth_read32, .read = omap_id_read,
omap_badwidth_read32, .write = omap_id_write,
omap_id_read, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUWriteMemoryFunc * const omap_id_writefn[] = { static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
omap_badwidth_write32,
omap_badwidth_write32,
omap_id_write,
};
static void omap_id_init(struct omap_mpu_state_s *mpu)
{ {
int iomemtype = cpu_register_io_memory(omap_id_readfn, memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN); "omap-id", 0x100000000ULL);
cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800); memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400); 0xfffe1800, 0x800);
if (!cpu_is_omap15xx(mpu)) memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000); memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
0xfffed400, 0x100);
memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
if (!cpu_is_omap15xx(mpu)) {
memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
&mpu->id_iomem, 0xfffe2000, 0x800);
memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
}
} }
/* MPUI Control (Dummy) */ /* MPUI Control (Dummy) */
static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) { switch (addr) {
case 0x00: /* CTRL */ case 0x00: /* CTRL */
return s->mpui_ctrl; return s->mpui_ctrl;
@ -1039,10 +1073,14 @@ static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_mpui_write(void *opaque, target_phys_addr_t addr, static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) { switch (addr) {
case 0x00: /* CTRL */ case 0x00: /* CTRL */
s->mpui_ctrl = value & 0x007fffff; s->mpui_ctrl = value & 0x007fffff;
@ -1064,16 +1102,10 @@ static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_mpui_readfn[] = { static const MemoryRegionOps omap_mpui_ops = {
omap_badwidth_read32, .read = omap_mpui_read,
omap_badwidth_read32, .write = omap_mpui_write,
omap_mpui_read, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_mpui_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_mpui_write,
}; };
static void omap_mpui_reset(struct omap_mpu_state_s *s) static void omap_mpui_reset(struct omap_mpu_state_s *s)
@ -1081,13 +1113,12 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
s->mpui_ctrl = 0x0003ff1b; s->mpui_ctrl = 0x0003ff1b;
} }
static void omap_mpui_init(target_phys_addr_t base, static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
struct omap_mpu_state_s *mpu) struct omap_mpu_state_s *mpu)
{ {
int iomemtype = cpu_register_io_memory(omap_mpui_readfn, memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN); "omap-mpui", 0x100);
memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
cpu_register_physical_memory(base, 0x100, iomemtype);
omap_mpui_reset(mpu); omap_mpui_reset(mpu);
} }
@ -1095,6 +1126,7 @@ static void omap_mpui_init(target_phys_addr_t base,
/* TIPB Bridges */ /* TIPB Bridges */
struct omap_tipb_bridge_s { struct omap_tipb_bridge_s {
qemu_irq abort; qemu_irq abort;
MemoryRegion iomem;
int width_intr; int width_intr;
uint16_t control; uint16_t control;
@ -1103,10 +1135,15 @@ struct omap_tipb_bridge_s {
uint16_t enh_control; uint16_t enh_control;
}; };
static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
if (size < 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) { switch (addr) {
case 0x00: /* TIPB_CNTL */ case 0x00: /* TIPB_CNTL */
return s->control; return s->control;
@ -1129,10 +1166,14 @@ static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
if (size < 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) { switch (addr) {
case 0x00: /* TIPB_CNTL */ case 0x00: /* TIPB_CNTL */
s->control = value & 0xffff; s->control = value & 0xffff;
@ -1163,16 +1204,10 @@ static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = { static const MemoryRegionOps omap_tipb_bridge_ops = {
omap_badwidth_read16, .read = omap_tipb_bridge_read,
omap_tipb_bridge_read, .write = omap_tipb_bridge_write,
omap_tipb_bridge_read, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = {
omap_badwidth_write16,
omap_tipb_bridge_write,
omap_tipb_bridge_write,
}; };
static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
@ -1183,19 +1218,19 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
s->enh_control = 0x000f; s->enh_control = 0x000f;
} }
static struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
qemu_irq abort_irq, omap_clk clk) MemoryRegion *memory, target_phys_addr_t base,
qemu_irq abort_irq, omap_clk clk)
{ {
int iomemtype;
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
g_malloc0(sizeof(struct omap_tipb_bridge_s)); g_malloc0(sizeof(struct omap_tipb_bridge_s));
s->abort = abort_irq; s->abort = abort_irq;
omap_tipb_bridge_reset(s); omap_tipb_bridge_reset(s);
iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn, memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN); "omap-tipb-bridge", 0x100);
cpu_register_physical_memory(base, 0x100, iomemtype); memory_region_add_subregion(memory, base, &s->iomem);
return s; return s;
} }
@ -3706,7 +3741,8 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
} }
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
unsigned long sdram_size,
const char *core) const char *core)
{ {
int i; int i;
@ -3772,21 +3808,21 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
soc_dma_port_add_mem_ram(s->dma, soc_dma_port_add_mem_ram(s->dma,
imif_base, OMAP_IMIF_BASE, s->sram_size); imif_base, OMAP_IMIF_BASE, s->sram_size);
s->timer[0] = omap_mpu_timer_init(0xfffec500, s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
s->irq[0][OMAP_INT_TIMER1], s->irq[0][OMAP_INT_TIMER1],
omap_findclk(s, "mputim_ck")); omap_findclk(s, "mputim_ck"));
s->timer[1] = omap_mpu_timer_init(0xfffec600, s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
s->irq[0][OMAP_INT_TIMER2], s->irq[0][OMAP_INT_TIMER2],
omap_findclk(s, "mputim_ck")); omap_findclk(s, "mputim_ck"));
s->timer[2] = omap_mpu_timer_init(0xfffec700, s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
s->irq[0][OMAP_INT_TIMER3], s->irq[0][OMAP_INT_TIMER3],
omap_findclk(s, "mputim_ck")); omap_findclk(s, "mputim_ck"));
s->wdt = omap_wd_timer_init(0xfffec800, s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
s->irq[0][OMAP_INT_WD_TIMER], s->irq[0][OMAP_INT_WD_TIMER],
omap_findclk(s, "armwdt_ck")); omap_findclk(s, "armwdt_ck"));
s->os_timer = omap_os_timer_init(0xfffb9000, s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
s->irq[1][OMAP_INT_OS_TIMER], s->irq[1][OMAP_INT_OS_TIMER],
omap_findclk(s, "clk32-kHz")); omap_findclk(s, "clk32-kHz"));
@ -3794,16 +3830,16 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
omap_dma_get_lcdch(s->dma), imif_base, emiff_base, omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
omap_findclk(s, "lcd_ck")); omap_findclk(s, "lcd_ck"));
omap_ulpd_pm_init(0xfffe0800, s); omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
omap_pin_cfg_init(0xfffe1000, s); omap_pin_cfg_init(system_memory, 0xfffe1000, s);
omap_id_init(s); omap_id_init(system_memory, s);
omap_mpui_init(0xfffec900, s); omap_mpui_init(system_memory, 0xfffec900, s);
s->private_tipb = omap_tipb_bridge_init(0xfffeca00, s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
s->irq[0][OMAP_INT_BRIDGE_PRIV], s->irq[0][OMAP_INT_BRIDGE_PRIV],
omap_findclk(s, "tipb_ck")); omap_findclk(s, "tipb_ck"));
s->public_tipb = omap_tipb_bridge_init(0xfffed300, s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
s->irq[0][OMAP_INT_BRIDGE_PUB], s->irq[0][OMAP_INT_BRIDGE_PUB],
omap_findclk(s, "tipb_ck")); omap_findclk(s, "tipb_ck"));

4
hw/omap_sx1.c
View File

@ -32,6 +32,7 @@
#include "arm-misc.h" #include "arm-misc.h"
#include "flash.h" #include "flash.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
/*****************************************************************************/ /*****************************************************************************/
/* Siemens SX1 Cellphone V1 */ /* Siemens SX1 Cellphone V1 */
@ -121,6 +122,7 @@ static void sx1_init(ram_addr_t ram_size,
const int version) const int version)
{ {
struct omap_mpu_state_s *cpu; struct omap_mpu_state_s *cpu;
MemoryRegion *address_space = get_system_memory();
int io; int io;
static uint32_t cs0val = 0x00213090; static uint32_t cs0val = 0x00213090;
static uint32_t cs1val = 0x00215070; static uint32_t cs1val = 0x00215070;
@ -135,7 +137,7 @@ static void sx1_init(ram_addr_t ram_size,
flash_size = flash2_size; flash_size = flash2_size;
} }
cpu = omap310_mpu_init(sx1_binfo.ram_size, cpu_model); cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */ /* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,

4
hw/palm.c
View File

@ -25,6 +25,7 @@
#include "arm-misc.h" #include "arm-misc.h"
#include "devices.h" #include "devices.h"
#include "loader.h" #include "loader.h"
#include "exec-memory.h"
static uint32_t static_readb(void *opaque, target_phys_addr_t offset) static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{ {
@ -198,6 +199,7 @@ static void palmte_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline, const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model) const char *initrd_filename, const char *cpu_model)
{ {
MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *cpu; struct omap_mpu_state_s *cpu;
int flash_size = 0x00800000; int flash_size = 0x00800000;
int sdram_size = palmte_binfo.ram_size; int sdram_size = palmte_binfo.ram_size;
@ -209,7 +211,7 @@ static void palmte_init(ram_addr_t ram_size,
int rom_size, rom_loaded = 0; int rom_size, rom_loaded = 0;
DisplayState *ds = get_displaystate(); DisplayState *ds = get_displaystate();
cpu = omap310_mpu_init(sdram_size, cpu_model); cpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
/* External Flash (EMIFS) */ /* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,