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target/arm: Use mte_check1 for sve LD1R

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-06-25 20:31:28 -07:00 committed by Peter Maydell
parent bba87d0a0f
commit 4ac430e1f1
1 changed files with 4 additions and 2 deletions
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6
target/arm/translate-sve.c
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@ -4892,7 +4892,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
unsigned esz = dtype_esz[a->dtype]; unsigned esz = dtype_esz[a->dtype];
unsigned msz = dtype_msz(a->dtype); unsigned msz = dtype_msz(a->dtype);
TCGLabel *over = gen_new_label(); TCGLabel *over = gen_new_label();
TCGv_i64 temp; TCGv_i64 temp, clean_addr;
/* If the guarding predicate has no bits set, no load occurs. */ /* If the guarding predicate has no bits set, no load occurs. */
if (psz <= 8) { if (psz <= 8) {
@ -4915,7 +4915,9 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
/* Load the data. */ /* Load the data. */
temp = tcg_temp_new_i64(); temp = tcg_temp_new_i64();
tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s), clean_addr = gen_mte_check1(s, temp, false, true, msz);
tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s),
s->be_data | dtype_mop[a->dtype]); s->be_data | dtype_mop[a->dtype]);
/* Broadcast to *all* elements. */ /* Broadcast to *all* elements. */