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target-arm: Remove remaining old cp15 infrastructure

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There are now no uses of the old cp15 infrastructure,
so it can be deleted.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-06-20 11:57:22 +00:00
parent 30b05bba11
commit 4a9a539ffb
3 changed files with 1 additions and 100 deletions
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39
target-arm/helper.c
View File

@ -1441,16 +1441,6 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
return 1;
}
void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
{
cpu_abort(env, "cp15 insn %08x\n", insn);
}
uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
{
cpu_abort(env, "cp15 insn %08x\n", insn);
}
/* These should probably raise undefined insn exceptions. */
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
@ -2177,35 +2167,6 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
return phys_addr;
}
void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
{
int op1;
int op2;
int crm;
op1 = (insn >> 21) & 7;
op2 = (insn >> 5) & 7;
crm = insn & 0xf;
/* ??? For debugging only. Should raise illegal instruction exception. */
cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
(insn >> 16) & 0xf, crm, op1, op2);
}
uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
{
int op1;
int op2;
int crm;
op1 = (insn >> 21) & 7;
op2 = (insn >> 5) & 7;
crm = insn & 0xf;
/* ??? For debugging only. Should raise illegal instruction exception. */
cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
(insn >> 16) & 0xf, crm, op1, op2);
return 0;
}
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
if ((env->uncached_cpsr & CPSR_M) == mode) {

3
target-arm/helper.h
View File

@ -59,9 +59,6 @@ DEF_HELPER_0(cpsr_read, i32)
DEF_HELPER_3(v7m_msr, void, env, i32, i32)
DEF_HELPER_2(v7m_mrs, i32, env, i32)
DEF_HELPER_3(set_cp15, void, env, i32, i32)
DEF_HELPER_2(get_cp15, i32, env, i32)
DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
DEF_HELPER_2(get_cp_reg, i32, env, ptr)
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)

57
target-arm/translate.c
View File

@ -2439,55 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
return 1;
}
/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
instruction is not defined. */
static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
{
uint32_t rd;
TCGv tmp, tmp2;
/* M profile cores use memory mapped registers instead of cp15. */
if (arm_feature(env, ARM_FEATURE_M))
return 1;
if ((insn & (1 << 25)) == 0) {
return 1;
}
if ((insn & (1 << 4)) == 0) {
/* cdp */
return 1;
}
if (IS_USER(s)) {
return 1;
}
rd = (insn >> 12) & 0xf;
tmp2 = tcg_const_i32(insn);
if (insn & ARM_CP_RW_BIT) {
tmp = tcg_temp_new_i32();
gen_helper_get_cp15(tmp, cpu_env, tmp2);
/* If the destination register is r15 then sets condition codes. */
if (rd != 15)
store_reg(s, rd, tmp);
else
tcg_temp_free_i32(tmp);
} else {
tmp = load_reg(s, rd);
gen_helper_set_cp15(cpu_env, tmp2, tmp);
tcg_temp_free_i32(tmp);
/* Normally we would always end the TB here, but Linux
* arch/arm/mach-pxa/sleep.S expects two instructions following
* an MMU enable to execute from cache. Imitate this behaviour. */
if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
(insn & 0x0fff0fff) != 0x0e010f10)
gen_lookup_tb(s);
}
tcg_temp_free_i32(tmp2);
return 0;
}
#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
#define VFP_SREG(insn, bigbit, smallbit) \
((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
@ -6388,16 +6339,8 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
return 0;
}
/* Fallback code: handle coprocessor registers not yet converted
* to ARMCPRegInfo.
*/
switch (cpnum) {
case 15:
return disas_cp15_insn (env, s, insn);
default:
return 1;
}
}
/* Store a 64-bit value to a register pair. Clobbers val. */