i.MX: Standardize i.MX CCM debug
The goal is to have debug code always compiled during build. We standardize all debug output on the following format: [QOM_TYPE_NAME]reporting_function: debug message The qemu_log_mask() output is following the same format as the above debug. Adding some missing qemu_log_mask call for bad registers. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 293e08f31cbb4df84d58f693243e61e770c73b3a.1445781957.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -16,14 +16,18 @@
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#define CKIH_FREQ 26000000 /* 26MHz crystal input */
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#define CKIL_FREQ 32768 /* nominal 32khz clock */
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//#define DEBUG_CCM 1
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#ifdef DEBUG_CCM
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#define DPRINTF(fmt, args...) \
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do { printf("%s: " fmt , TYPE_IMX_CCM, ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...) do {} while (0)
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#ifndef DEBUG_IMX_CCM
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#define DEBUG_IMX_CCM 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_CCM) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_CCM, \
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__func__, ##args); \
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} \
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} while (0)
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static int imx_ccm_post_load(void *opaque, int version_id);
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static const VMStateDescription vmstate_imx_ccm = {
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@ -109,7 +113,7 @@ static void update_clocks(IMXCCMState *s)
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s->hsp_clk_freq = s->mcu_clk_freq / (1 + EXTRACT(s->pdr0, HSP));
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s->ipg_clk_freq = s->hsp_clk_freq / (1 + EXTRACT(s->pdr0, IPG));
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DPRINTF("%s: mcu %uMHz, HSP %uMHz, IPG %uHz\n", __func__,
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DPRINTF("mcu %uMHz, HSP %uMHz, IPG %uHz\n",
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s->mcu_clk_freq / 1000000,
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s->hsp_clk_freq / 1000000,
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s->ipg_clk_freq);
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@ -135,7 +139,8 @@ static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
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{
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IMXCCMState *s = (IMXCCMState *)opaque;
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DPRINTF("%s(offset=%x)", __func__, offset >> 2);
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DPRINTF("(offset=0x%" HWADDR_PRIx ")\n", offset);
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switch (offset >> 2) {
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case 0: /* CCMR */
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DPRINTF(" ccmr = 0x%x\n", s->ccmr);
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@ -166,9 +171,11 @@ static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
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case 23:
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DPRINTF(" pcmr0 = 0x%x\n", s->pmcr0);
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return s->pmcr0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_CCM, __func__, offset);
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return 0;
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}
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DPRINTF(" return 0\n");
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return 0;
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}
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static void imx_ccm_write(void *opaque, hwaddr offset,
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@ -176,8 +183,9 @@ static void imx_ccm_write(void *opaque, hwaddr offset,
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{
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IMXCCMState *s = (IMXCCMState *)opaque;
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DPRINTF("%s(offset=%x, value = %x)\n", __func__,
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offset >> 2, (unsigned int)value);
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DPRINTF("(offset=0x%" HWADDR_PRIx ", value = 0x%x)\n",
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offset, (unsigned int)value);
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switch (offset >> 2) {
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case 0:
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s->ccmr = CCMR_FPMF | (value & 0x3b6fdfff);
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@ -205,6 +213,8 @@ static void imx_ccm_write(void *opaque, hwaddr offset,
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_CCM, __func__, offset);
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return;
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}
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update_clocks(s);
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