target-arm: A64: add support for ld/st pair
This patch support the basic load and store pair instructions and includes the generic helper functions: * do_gpr_st() * do_fp_st() * do_gpr_ld() * do_fp_ld() * read_cpu_reg_sp() * gen_check_sp_alignment() The last function gen_check_sp_alignment() is a NULL op currently but put in place to make it easy to add SP alignment checking later. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
f976b09ea2
commit
4a08d4758f
@ -99,6 +99,15 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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cpu_fprintf(f, "\n");
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}
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static int get_mem_index(DisasContext *s)
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{
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#ifdef CONFIG_USER_ONLY
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return 1;
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#else
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return s->user;
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#endif
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}
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void gen_a64_set_pc_im(uint64_t val)
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{
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tcg_gen_movi_i64(cpu_pc, val);
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@ -250,6 +259,17 @@ static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
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return v;
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}
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static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
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{
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TCGv_i64 v = new_tmp_a64(s);
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if (sf) {
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tcg_gen_mov_i64(v, cpu_X[reg]);
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} else {
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tcg_gen_ext32u_i64(v, cpu_X[reg]);
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}
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return v;
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}
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/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
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* than the 32 bit equivalent.
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*/
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@ -277,6 +297,126 @@ static inline void gen_logic_CC(int sf, TCGv_i64 result)
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tcg_gen_movi_i32(cpu_VF, 0);
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}
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/*
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* Load/Store generators
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*/
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/*
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* Store from GPR register to memory
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*/
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static void do_gpr_st(DisasContext *s, TCGv_i64 source,
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TCGv_i64 tcg_addr, int size)
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{
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g_assert(size <= 3);
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tcg_gen_qemu_st_i64(source, tcg_addr, get_mem_index(s), MO_TE + size);
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}
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/*
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* Load from memory to GPR register
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*/
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static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
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int size, bool is_signed, bool extend)
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{
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TCGMemOp memop = MO_TE + size;
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g_assert(size <= 3);
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if (is_signed) {
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memop += MO_SIGN;
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}
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tcg_gen_qemu_ld_i64(dest, tcg_addr, get_mem_index(s), memop);
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if (extend && is_signed) {
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g_assert(size < 3);
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tcg_gen_ext32u_i64(dest, dest);
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}
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}
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/*
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* Store from FP register to memory
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*/
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static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
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{
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/* This writes the bottom N bits of a 128 bit wide vector to memory */
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int freg_offs = offsetof(CPUARMState, vfp.regs[srcidx * 2]);
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TCGv_i64 tmp = tcg_temp_new_i64();
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if (size < 4) {
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switch (size) {
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case 0:
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tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs);
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break;
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case 1:
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tcg_gen_ld16u_i64(tmp, cpu_env, freg_offs);
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break;
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case 2:
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tcg_gen_ld32u_i64(tmp, cpu_env, freg_offs);
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break;
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case 3:
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tcg_gen_ld_i64(tmp, cpu_env, freg_offs);
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break;
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}
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tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size);
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} else {
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TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
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tcg_gen_ld_i64(tmp, cpu_env, freg_offs);
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tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ);
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tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s));
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tcg_gen_ld_i64(tmp, cpu_env, freg_offs + sizeof(float64));
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tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
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tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ);
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tcg_temp_free_i64(tcg_hiaddr);
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}
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tcg_temp_free_i64(tmp);
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}
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/*
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* Load from memory to FP register
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*/
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static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
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{
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/* This always zero-extends and writes to a full 128 bit wide vector */
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int freg_offs = offsetof(CPUARMState, vfp.regs[destidx * 2]);
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TCGv_i64 tmplo = tcg_temp_new_i64();
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TCGv_i64 tmphi;
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if (size < 4) {
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TCGMemOp memop = MO_TE + size;
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tmphi = tcg_const_i64(0);
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tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
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} else {
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TCGv_i64 tcg_hiaddr;
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tmphi = tcg_temp_new_i64();
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tcg_hiaddr = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ);
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tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
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tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ);
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tcg_temp_free_i64(tcg_hiaddr);
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}
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tcg_gen_st_i64(tmplo, cpu_env, freg_offs);
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tcg_gen_st_i64(tmphi, cpu_env, freg_offs + sizeof(float64));
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tcg_temp_free_i64(tmplo);
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tcg_temp_free_i64(tmphi);
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}
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static inline void gen_check_sp_alignment(DisasContext *s)
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{
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/* The AArch64 architecture mandates that (if enabled via PSTATE
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* or SCTLR bits) there is a check that SP is 16-aligned on every
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* SP-relative load or store (with an exception generated if it is not).
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* In line with general QEMU practice regarding misaligned accesses,
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* we omit these checks for the sake of guest program performance.
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* This function is provided as a hook so we can more easily add these
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* checks in future (possibly as a "favour catching guest program bugs
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* over speed" user selectable option).
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*/
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}
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/*
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* the instruction disassembly implemented here matches
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* the instruction encoding classifications in chapter 3 (C3)
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@ -620,10 +760,145 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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}
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/* Load/store pair (all forms) */
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/*
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* C5.6.80 LDNP (Load Pair - non-temporal hint)
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* C5.6.81 LDP (Load Pair - non vector)
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* C5.6.82 LDPSW (Load Pair Signed Word - non vector)
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* C5.6.176 STNP (Store Pair - non-temporal hint)
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* C5.6.177 STP (Store Pair - non vector)
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* C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
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* C6.3.165 LDP (Load Pair of SIMD&FP)
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* C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
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* C6.3.284 STP (Store Pair of SIMD&FP)
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*
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* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
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* +-----+-------+---+---+-------+---+-----------------------------+
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* | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
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* +-----+-------+---+---+-------+---+-------+-------+------+------+
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*
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* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
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* LDPSW 01
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* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
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* V: 0 -> GPR, 1 -> Vector
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* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
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* 10 -> signed offset, 11 -> pre-index
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* L: 0 -> Store 1 -> Load
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*
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* Rt, Rt2 = GPR or SIMD registers to be stored
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* Rn = general purpose register containing address
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* imm7 = signed offset (multiple of 4 or 8 depending on size)
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*/
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static void disas_ldst_pair(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rt = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int rt2 = extract32(insn, 10, 5);
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int64_t offset = sextract32(insn, 15, 7);
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int index = extract32(insn, 23, 2);
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bool is_vector = extract32(insn, 26, 1);
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bool is_load = extract32(insn, 22, 1);
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int opc = extract32(insn, 30, 2);
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bool is_signed = false;
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bool postindex = false;
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bool wback = false;
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TCGv_i64 tcg_addr; /* calculated address */
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int size;
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if (opc == 3) {
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unallocated_encoding(s);
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return;
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}
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if (is_vector) {
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size = 2 + opc;
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} else {
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size = 2 + extract32(opc, 1, 1);
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is_signed = extract32(opc, 0, 1);
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if (!is_load && is_signed) {
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unallocated_encoding(s);
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return;
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}
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}
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switch (index) {
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case 1: /* post-index */
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postindex = true;
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wback = true;
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break;
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case 0:
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/* signed offset with "non-temporal" hint. Since we don't emulate
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* caches we don't care about hints to the cache system about
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* data access patterns, and handle this identically to plain
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* signed offset.
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*/
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if (is_signed) {
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/* There is no non-temporal-hint version of LDPSW */
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unallocated_encoding(s);
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return;
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}
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postindex = false;
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break;
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case 2: /* signed offset, rn not updated */
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postindex = false;
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break;
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case 3: /* pre-index */
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postindex = false;
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wback = true;
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break;
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}
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offset <<= size;
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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tcg_addr = read_cpu_reg_sp(s, rn, 1);
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if (!postindex) {
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tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
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}
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if (is_vector) {
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if (is_load) {
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do_fp_ld(s, rt, tcg_addr, size);
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} else {
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do_fp_st(s, rt, tcg_addr, size);
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}
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} else {
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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if (is_load) {
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do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
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} else {
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do_gpr_st(s, tcg_rt, tcg_addr, size);
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}
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}
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tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
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if (is_vector) {
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if (is_load) {
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do_fp_ld(s, rt2, tcg_addr, size);
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} else {
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do_fp_st(s, rt2, tcg_addr, size);
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}
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} else {
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TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
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if (is_load) {
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do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
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} else {
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do_gpr_st(s, tcg_rt2, tcg_addr, size);
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}
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}
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if (wback) {
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if (postindex) {
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tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
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} else {
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tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
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}
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tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
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}
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}
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/* Load/store register (all forms) */
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