target/sparc: Split ver from env->fsr
This field is read-only. It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-17-richard.henderson@linaro.org>
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@ -368,7 +368,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "Fujitsu MB86904",
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.name = "Fujitsu MB86904",
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.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
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.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.mmu_bm = 0x00004000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_ctpr_mask = 0x00ffffc0,
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@ -381,7 +381,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "Fujitsu MB86907",
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.name = "Fujitsu MB86907",
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.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
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.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.mmu_bm = 0x00004000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_ctpr_mask = 0xffffffc0,
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@ -394,7 +394,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI MicroSparc I",
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.name = "TI MicroSparc I",
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.iu_version = 0x41000000,
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.iu_version = 0x41000000,
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.fpu_version = 4 << 17,
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.fpu_version = 4 << FSR_VER_SHIFT,
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.mmu_version = 0x41000000,
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.mmu_version = 0x41000000,
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.mmu_bm = 0x00004000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_ctpr_mask = 0x007ffff0,
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@ -407,7 +407,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI MicroSparc II",
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.name = "TI MicroSparc II",
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.iu_version = 0x42000000,
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.fpu_version = 4 << FSR_VER_SHIFT,
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.mmu_version = 0x02000000,
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.mmu_version = 0x02000000,
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.mmu_bm = 0x00004000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_ctpr_mask = 0x00ffffc0,
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@ -420,7 +420,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI MicroSparc IIep",
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.name = "TI MicroSparc IIep",
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.iu_version = 0x42000000,
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.fpu_version = 4 << FSR_VER_SHIFT,
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.mmu_version = 0x04000000,
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.mmu_version = 0x04000000,
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.mmu_bm = 0x00004000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_ctpr_mask = 0x00ffffc0,
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@ -433,7 +433,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI SuperSparc 40", /* STP1020NPGA */
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.name = "TI SuperSparc 40", /* STP1020NPGA */
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.iu_version = 0x41000000, /* SuperSPARC 2.x */
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.iu_version = 0x41000000, /* SuperSPARC 2.x */
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.fpu_version = 0 << 17,
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.fpu_version = 0 << FSR_VER_SHIFT,
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.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
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.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_ctpr_mask = 0xffffffc0,
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@ -446,7 +446,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI SuperSparc 50", /* STP1020PGA */
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.name = "TI SuperSparc 50", /* STP1020PGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.fpu_version = 0 << FSR_VER_SHIFT,
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_ctpr_mask = 0xffffffc0,
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@ -459,7 +459,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI SuperSparc 51",
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.name = "TI SuperSparc 51",
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.fpu_version = 0 << FSR_VER_SHIFT,
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_ctpr_mask = 0xffffffc0,
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@ -473,7 +473,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI SuperSparc 60", /* STP1020APGA */
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.name = "TI SuperSparc 60", /* STP1020APGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.fpu_version = 0 << FSR_VER_SHIFT,
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_ctpr_mask = 0xffffffc0,
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@ -486,7 +486,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI SuperSparc 61",
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.name = "TI SuperSparc 61",
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.iu_version = 0x44000000, /* SuperSPARC 3.x */
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.iu_version = 0x44000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.fpu_version = 0 << FSR_VER_SHIFT,
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_ctpr_mask = 0xffffffc0,
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@ -500,7 +500,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "TI SuperSparc II",
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.name = "TI SuperSparc II",
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.iu_version = 0x40000000, /* SuperSPARC II 1.x */
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.iu_version = 0x40000000, /* SuperSPARC II 1.x */
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.fpu_version = 0 << 17,
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.fpu_version = 0 << FSR_VER_SHIFT,
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.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
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.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_ctpr_mask = 0xffffffc0,
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@ -514,7 +514,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "LEON2",
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.name = "LEON2",
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.iu_version = 0xf2000000,
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.iu_version = 0xf2000000,
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
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.mmu_version = 0xf2000000,
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.mmu_version = 0xf2000000,
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.mmu_bm = 0x00004000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_ctpr_mask = 0x007ffff0,
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@ -527,7 +527,7 @@ static const sparc_def_t sparc_defs[] = {
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{
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{
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.name = "LEON3",
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.name = "LEON3",
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.iu_version = 0xf3000000,
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.iu_version = 0xf3000000,
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
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.mmu_version = 0xf3000000,
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.mmu_version = 0xf3000000,
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.mmu_bm = 0x00000000,
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.mmu_bm = 0x00000000,
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.mmu_ctpr_mask = 0xfffffffc,
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.mmu_ctpr_mask = 0xfffffffc,
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@ -786,7 +786,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
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#endif
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#endif
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env->version = env->def.iu_version;
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env->version = env->def.iu_version;
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env->fsr = env->def.fpu_version;
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env->nwindows = env->def.nwindows;
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env->nwindows = env->def.nwindows;
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#if !defined(TARGET_SPARC64)
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#if !defined(TARGET_SPARC64)
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env->mmuregs[0] |= env->def.mmu_version;
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env->mmuregs[0] |= env->def.mmu_version;
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@ -191,6 +191,9 @@ enum {
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#define FSR_NXC (1ULL << 0)
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#define FSR_NXC (1ULL << 0)
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#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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#define FSR_VER_SHIFT 17
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#define FSR_VER_MASK (7 << FSR_VER_SHIFT)
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#define FSR_FTT2 (1ULL << 16)
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#define FSR_FTT2 (1ULL << 16)
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#define FSR_FTT1 (1ULL << 15)
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#define FSR_FTT1 (1ULL << 15)
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#define FSR_FTT0 (1ULL << 14)
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#define FSR_FTT0 (1ULL << 14)
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@ -349,7 +349,12 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1);
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target_ulong cpu_get_fsr(CPUSPARCState *env)
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target_ulong cpu_get_fsr(CPUSPARCState *env)
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{
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{
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return env->fsr;
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target_ulong fsr = env->fsr;
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/* VER is kept completely separate until re-assembly. */
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fsr |= env->def.fpu_version;
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return fsr;
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}
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}
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target_ulong helper_get_fsr(CPUSPARCState *env)
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target_ulong helper_get_fsr(CPUSPARCState *env)
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@ -361,7 +366,7 @@ static void set_fsr_nonsplit(CPUSPARCState *env, target_ulong fsr)
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{
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{
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int rnd_mode;
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int rnd_mode;
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env->fsr = fsr;
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env->fsr = fsr & ~FSR_VER_MASK;
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switch (fsr & FSR_RD_MASK) {
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switch (fsr & FSR_RD_MASK) {
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case FSR_RD_NEAREST:
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case FSR_RD_NEAREST:
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