fdc-test: Test state for existing cases more thoroughly
This just adds a few additional checks of the MSR and interrupt pin to the already existing test cases. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1432214378-31891-9-git-send-email-kwolf@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
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@ -218,6 +218,10 @@ static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0)
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inb(FLOPPY_BASE + reg_fifo);
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inb(FLOPPY_BASE + reg_fifo);
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}
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}
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msr = inb(FLOPPY_BASE + reg_msr);
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assert_bit_set(msr, BUSY | RQM | DIO);
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g_assert(get_irq(FLOPPY_IRQ));
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st0 = floppy_recv();
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st0 = floppy_recv();
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if (st0 != expected_st0) {
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if (st0 != expected_st0) {
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ret = 1;
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ret = 1;
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@ -228,8 +232,15 @@ static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0)
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floppy_recv();
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floppy_recv();
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floppy_recv();
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floppy_recv();
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floppy_recv();
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floppy_recv();
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g_assert(get_irq(FLOPPY_IRQ));
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floppy_recv();
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floppy_recv();
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/* Check that we're back in command phase */
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msr = inb(FLOPPY_BASE + reg_msr);
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assert_bit_clear(msr, BUSY | DIO);
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assert_bit_set(msr, RQM);
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g_assert(!get_irq(FLOPPY_IRQ));
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return ret;
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return ret;
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}
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}
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@ -403,6 +414,7 @@ static void test_read_id(void)
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uint8_t head = 0;
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uint8_t head = 0;
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uint8_t cyl;
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uint8_t cyl;
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uint8_t st0;
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uint8_t st0;
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uint8_t msr;
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/* Seek to track 0 and check with READ ID */
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/* Seek to track 0 and check with READ ID */
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send_seek(0);
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send_seek(0);
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@ -411,18 +423,29 @@ static void test_read_id(void)
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g_assert(!get_irq(FLOPPY_IRQ));
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g_assert(!get_irq(FLOPPY_IRQ));
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floppy_send(head << 2 | drive);
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floppy_send(head << 2 | drive);
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msr = inb(FLOPPY_BASE + reg_msr);
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if (!get_irq(FLOPPY_IRQ)) {
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assert_bit_set(msr, BUSY);
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assert_bit_clear(msr, RQM);
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}
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while (!get_irq(FLOPPY_IRQ)) {
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while (!get_irq(FLOPPY_IRQ)) {
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/* qemu involves a timer with READ ID... */
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/* qemu involves a timer with READ ID... */
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clock_step(1000000000LL / 50);
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clock_step(1000000000LL / 50);
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}
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}
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msr = inb(FLOPPY_BASE + reg_msr);
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assert_bit_set(msr, BUSY | RQM | DIO);
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st0 = floppy_recv();
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st0 = floppy_recv();
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floppy_recv();
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floppy_recv();
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floppy_recv();
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floppy_recv();
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cyl = floppy_recv();
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cyl = floppy_recv();
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head = floppy_recv();
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head = floppy_recv();
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floppy_recv();
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floppy_recv();
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g_assert(get_irq(FLOPPY_IRQ));
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floppy_recv();
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floppy_recv();
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g_assert(!get_irq(FLOPPY_IRQ));
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g_assert_cmpint(cyl, ==, 0);
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g_assert_cmpint(cyl, ==, 0);
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g_assert_cmpint(head, ==, 0);
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g_assert_cmpint(head, ==, 0);
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@ -443,18 +466,29 @@ static void test_read_id(void)
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g_assert(!get_irq(FLOPPY_IRQ));
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g_assert(!get_irq(FLOPPY_IRQ));
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floppy_send(head << 2 | drive);
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floppy_send(head << 2 | drive);
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msr = inb(FLOPPY_BASE + reg_msr);
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if (!get_irq(FLOPPY_IRQ)) {
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assert_bit_set(msr, BUSY);
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assert_bit_clear(msr, RQM);
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}
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while (!get_irq(FLOPPY_IRQ)) {
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while (!get_irq(FLOPPY_IRQ)) {
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/* qemu involves a timer with READ ID... */
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/* qemu involves a timer with READ ID... */
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clock_step(1000000000LL / 50);
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clock_step(1000000000LL / 50);
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}
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}
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msr = inb(FLOPPY_BASE + reg_msr);
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assert_bit_set(msr, BUSY | RQM | DIO);
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st0 = floppy_recv();
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st0 = floppy_recv();
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floppy_recv();
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floppy_recv();
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floppy_recv();
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floppy_recv();
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cyl = floppy_recv();
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cyl = floppy_recv();
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head = floppy_recv();
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head = floppy_recv();
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floppy_recv();
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floppy_recv();
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g_assert(get_irq(FLOPPY_IRQ));
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floppy_recv();
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floppy_recv();
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g_assert(!get_irq(FLOPPY_IRQ));
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g_assert_cmpint(cyl, ==, 8);
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g_assert_cmpint(cyl, ==, 8);
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g_assert_cmpint(head, ==, 1);
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g_assert_cmpint(head, ==, 1);
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