tcg/riscv: Use tcg_use_softmmu
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
cf0ed30eb1
commit
4944d35910
@ -1245,105 +1245,110 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
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aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
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a_mask = (1u << aa.align) - 1;
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#ifdef CONFIG_SOFTMMU
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unsigned s_bits = opc & MO_SIZE;
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unsigned s_mask = (1u << s_bits) - 1;
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int mem_index = get_mmuidx(oi);
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int fast_ofs = tlb_mask_table_ofs(s, mem_index);
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int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
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int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
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int compare_mask;
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TCGReg addr_adj;
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if (tcg_use_softmmu) {
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unsigned s_bits = opc & MO_SIZE;
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unsigned s_mask = (1u << s_bits) - 1;
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int mem_index = get_mmuidx(oi);
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int fast_ofs = tlb_mask_table_ofs(s, mem_index);
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int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
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int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
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int compare_mask;
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TCGReg addr_adj;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
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tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
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tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
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/*
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* For aligned accesses, we check the first byte and include the alignment
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* bits within the address. For unaligned access, we check that we don't
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* cross pages using the address of the last byte of the access.
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*/
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addr_adj = addr_reg;
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if (a_mask < s_mask) {
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addr_adj = TCG_REG_TMP0;
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tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI,
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addr_adj, addr_reg, s_mask - a_mask);
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}
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compare_mask = s->page_mask | a_mask;
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if (compare_mask == sextreg(compare_mask, 0, 12)) {
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tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask);
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} else {
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tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask);
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tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj);
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}
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/* Load the tlb comparator and the addend. */
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QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
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tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
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is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
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offsetof(CPUTLBEntry, addend));
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/* Compare masked address with the TLB entry. */
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
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/* TLB Hit - translate address using addend. */
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if (addr_type != TCG_TYPE_I32) {
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tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
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} else if (have_zba) {
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tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
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} else {
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tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
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tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TMP2);
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}
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*pbase = TCG_REG_TMP0;
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#else
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TCGReg base;
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if (a_mask) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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/* We are expecting alignment max 7, so we can always use andi. */
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tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12));
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tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
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}
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tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
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tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
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if (guest_base != 0) {
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base = TCG_REG_TMP0;
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if (addr_type != TCG_TYPE_I32) {
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tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG);
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} else if (have_zba) {
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tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG);
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} else {
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tcg_out_ext32u(s, base, addr_reg);
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tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
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/*
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* For aligned accesses, we check the first byte and include the
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* alignment bits within the address. For unaligned access, we
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* check that we don't cross pages using the address of the last
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* byte of the access.
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*/
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addr_adj = addr_reg;
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if (a_mask < s_mask) {
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addr_adj = TCG_REG_TMP0;
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tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI,
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addr_adj, addr_reg, s_mask - a_mask);
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}
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} else if (addr_type != TCG_TYPE_I32) {
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base = addr_reg;
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compare_mask = s->page_mask | a_mask;
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if (compare_mask == sextreg(compare_mask, 0, 12)) {
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tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask);
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} else {
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tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask);
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tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj);
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}
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/* Load the tlb comparator and the addend. */
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QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
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tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
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is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
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offsetof(CPUTLBEntry, addend));
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/* Compare masked address with the TLB entry. */
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
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/* TLB Hit - translate address using addend. */
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if (addr_type != TCG_TYPE_I32) {
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tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
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} else if (have_zba) {
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tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0,
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addr_reg, TCG_REG_TMP2);
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} else {
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tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
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tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0,
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TCG_REG_TMP0, TCG_REG_TMP2);
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}
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*pbase = TCG_REG_TMP0;
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} else {
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base = TCG_REG_TMP0;
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tcg_out_ext32u(s, base, addr_reg);
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TCGReg base;
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if (a_mask) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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/* We are expecting alignment max 7, so we can always use andi. */
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tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12));
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tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask);
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
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}
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if (guest_base != 0) {
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base = TCG_REG_TMP0;
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if (addr_type != TCG_TYPE_I32) {
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tcg_out_opc_reg(s, OPC_ADD, base, addr_reg,
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TCG_GUEST_BASE_REG);
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} else if (have_zba) {
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tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg,
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TCG_GUEST_BASE_REG);
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} else {
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tcg_out_ext32u(s, base, addr_reg);
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tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
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}
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} else if (addr_type != TCG_TYPE_I32) {
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base = addr_reg;
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} else {
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base = TCG_REG_TMP0;
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tcg_out_ext32u(s, base, addr_reg);
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}
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*pbase = base;
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}
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*pbase = base;
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#endif
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return ldst;
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}
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@ -2075,12 +2080,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
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}
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#if !defined(CONFIG_SOFTMMU)
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if (guest_base) {
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if (!tcg_use_softmmu && guest_base) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
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tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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}
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#endif
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/* Call generated code */
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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