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target/riscv: rvv-1.0: Add Zve64f support for load and store insns

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All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:06 +08:00 committed by Alistair Francis
parent c7a26fb2f6
commit 494104093f
1 changed files with 15 additions and 4 deletions
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19
target/riscv/insn_trans/trans_rvv.c.inc
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@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
uint8_t eew)
{
int8_t emul = eew - s->sew + s->lmul;
return (emul >= -3 && emul <= 3) &&
require_align(vs2, emul) &&
require_align(vd, s->lmul) &&
require_nf(vd, nf, s->lmul);
bool ret = (emul >= -3 && emul <= 3) &&
require_align(vs2, emul) &&
require_align(vd, s->lmul) &&
require_nf(vd, nf, s->lmul);
/*
* All Zve* extensions support all vector load and store instructions,
* except Zve64* extensions do not support EEW=64 for index values
* when XLEN=32. (Section 18.2)
*/
if (get_xl(s) == MXL_RV32) {
ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
}
return ret;
}
/*