target/sh4: Convert to DisasJumpType
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170907185057.23421-3-richard.henderson@linaro.org> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson
Aurelien Jarno
parent
f85da3081d
commit
4834871bc9
@ -25,10 +25,9 @@
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#include "exec/exec-all.h"
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#include "tcg-op.h"
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "exec/translator.h"
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#include "trace-tcg.h"
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#include "exec/log.h"
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@ -39,7 +38,7 @@ typedef struct DisasContext {
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uint16_t opcode;
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uint32_t tbflags; /* should stay unmodified during the TB translation */
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uint32_t envflags; /* should stay in sync with env->flags using TCG ops */
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int bstate;
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DisasJumpType bstate;
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int memidx;
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int gbank;
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int fbank;
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@ -55,14 +54,10 @@ typedef struct DisasContext {
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#define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
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#endif
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enum {
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BS_NONE = 0, /* We go out of the TB without reaching a branch or an
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* exception condition
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*/
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BS_STOP = 1, /* We want to stop translation for any reason */
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BS_BRANCH = 2, /* We reached a branch condition */
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BS_EXCP = 3, /* We reached an exception condition */
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};
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/* Target-specific values for ctx->bstate. */
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/* We want to exit back to the cpu loop for some reason.
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Usually this is to recognize interrupts immediately. */
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#define DISAS_STOP DISAS_TARGET_0
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/* global register indexes */
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static TCGv cpu_gregs[32];
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@ -258,6 +253,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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ctx->bstate = DISAS_NORETURN;
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}
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static void gen_jump(DisasContext * ctx)
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@ -304,7 +300,7 @@ static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,
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gen_goto_tb(ctx, 0, dest);
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gen_set_label(l1);
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gen_goto_tb(ctx, 1, ctx->pc + 2);
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ctx->bstate = BS_BRANCH;
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ctx->bstate = DISAS_NORETURN;
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}
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/* Delayed conditional jump (bt or bf) */
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@ -327,6 +323,7 @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
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gen_jump(ctx);
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gen_set_label(l1);
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ctx->bstate = DISAS_NEXT;
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return;
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}
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@ -468,7 +465,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
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ctx->envflags |= DELAY_SLOT_RTE;
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ctx->delayed_pc = (uint32_t) - 1;
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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return;
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case 0x0058: /* sets */
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tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S));
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@ -479,17 +476,17 @@ static void _decode_opc(DisasContext * ctx)
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case 0xfbfd: /* frchg */
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CHECK_FPSCR_PR_0
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tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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return;
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case 0xf3fd: /* fschg */
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CHECK_FPSCR_PR_0
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tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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return;
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case 0xf7fd: /* fpchg */
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CHECK_SH4A
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tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR);
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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return;
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case 0x0009: /* nop */
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return;
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@ -524,7 +521,7 @@ static void _decode_opc(DisasContext * ctx)
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region (stored in R0) in the next TB. */
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if (B11_8 == 15 && B7_0s < 0 && (tb_cflags(ctx->tb) & CF_PARALLEL)) {
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ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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}
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#endif
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tcg_gen_movi_i32(REG(B11_8), B7_0s);
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@ -1310,7 +1307,7 @@ static void _decode_opc(DisasContext * ctx)
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imm = tcg_const_i32(B7_0);
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gen_helper_trapa(cpu_env, imm);
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tcg_temp_free(imm);
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ctx->bstate = BS_EXCP;
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ctx->bstate = DISAS_NORETURN;
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}
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return;
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case 0xc800: /* tst #imm,R0 */
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@ -1419,7 +1416,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3);
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gen_write_sr(val);
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tcg_temp_free(val);
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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}
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return;
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case 0x4007: /* ldc.l @Rm+,SR */
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@ -1431,7 +1428,7 @@ static void _decode_opc(DisasContext * ctx)
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gen_write_sr(val);
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tcg_temp_free(val);
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tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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}
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return;
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case 0x0002: /* stc SR,Rn */
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@ -1493,7 +1490,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0x406a: /* lds Rm,FPSCR */
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CHECK_FPU_ENABLED
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gen_helper_ld_fpscr(cpu_env, REG(B11_8));
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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return;
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case 0x4066: /* lds.l @Rm+,FPSCR */
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CHECK_FPU_ENABLED
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@ -1503,7 +1500,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
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gen_helper_ld_fpscr(cpu_env, addr);
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tcg_temp_free(addr);
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ctx->bstate = BS_STOP;
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ctx->bstate = DISAS_STOP;
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}
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return;
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case 0x006a: /* sts FPSCR,Rn */
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@ -1841,7 +1838,7 @@ static void _decode_opc(DisasContext * ctx)
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gen_save_cpu_state(ctx, true);
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gen_helper_raise_illegal_instruction(cpu_env);
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}
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ctx->bstate = BS_EXCP;
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ctx->bstate = DISAS_NORETURN;
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return;
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do_fpu_disabled:
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@ -1851,7 +1848,7 @@ static void _decode_opc(DisasContext * ctx)
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} else {
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gen_helper_raise_fpu_disable(cpu_env);
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}
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ctx->bstate = BS_EXCP;
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ctx->bstate = DISAS_NORETURN;
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return;
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}
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@ -1877,7 +1874,6 @@ static void decode_opc(DisasContext * ctx)
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ctx->envflags &= ~GUSA_MASK;
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tcg_gen_movi_i32(cpu_flags, ctx->envflags);
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ctx->bstate = BS_BRANCH;
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if (old_flags & DELAY_SLOT_CONDITIONAL) {
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gen_delayed_conditional_jump(ctx);
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} else {
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@ -2248,7 +2244,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
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ctx->envflags |= GUSA_EXCLUSIVE;
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gen_save_cpu_state(ctx, false);
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gen_helper_exclusive(cpu_env);
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ctx->bstate = BS_EXCP;
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ctx->bstate = DISAS_NORETURN;
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/* We're not executing an instruction, but we must report one for the
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purposes of accounting within the TB. We might as well report the
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@ -2271,7 +2267,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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ctx.pc = pc_start;
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ctx.tbflags = (uint32_t)tb->flags;
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ctx.envflags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
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ctx.bstate = BS_NONE;
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ctx.bstate = DISAS_NEXT;
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ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
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/* We don't know if the delayed pc came from a dynamic or static branch,
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so assume it is a dynamic branch. */
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@ -2309,7 +2305,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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}
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#endif
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while (ctx.bstate == BS_NONE
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while (ctx.bstate == DISAS_NEXT
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&& num_insns < max_insns
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&& !tcg_op_buf_full()) {
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tcg_gen_insn_start(ctx.pc, ctx.envflags);
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@ -2319,7 +2315,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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/* We have hit a breakpoint - make sure PC is up-to-date */
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gen_save_cpu_state(&ctx, true);
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gen_helper_debug(cpu_env);
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ctx.bstate = BS_EXCP;
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ctx.bstate = DISAS_NORETURN;
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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@ -2350,19 +2346,18 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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gen_helper_debug(cpu_env);
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} else {
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switch (ctx.bstate) {
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case BS_STOP:
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case DISAS_STOP:
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gen_save_cpu_state(&ctx, true);
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tcg_gen_exit_tb(0);
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break;
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case BS_NONE:
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case DISAS_NEXT:
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gen_save_cpu_state(&ctx, false);
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gen_goto_tb(&ctx, 0, ctx.pc);
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break;
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case BS_EXCP:
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/* fall through */
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case BS_BRANCH:
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default:
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case DISAS_NORETURN:
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break;
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default:
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g_assert_not_reached();
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}
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}
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