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esp: fix interrupt register read

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Read of interrupt register should clear it and also sequence step and status.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Blue Swirl 2009-07-31 07:26:44 +00:00 committed by Anthony Liguori
parent b9369a384b
commit 477806703a
1 changed files with 9 additions and 4 deletions
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13
hw/esp.c
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@ -422,7 +422,7 @@ static void parent_esp_reset(void *opaque, int irq, int level)
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{ {
ESPState *s = opaque; ESPState *s = opaque;
uint32_t saddr; uint32_t saddr, old_val;
saddr = addr >> s->it_shift; saddr = addr >> s->it_shift;
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
@ -445,10 +445,15 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
} }
break; break;
case ESP_RINTR: case ESP_RINTR:
// Clear interrupt/error status bits /* Clear sequence step, interrupt register and all status bits
s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE); except TC */
old_val = s->rregs[ESP_RINTR];
s->rregs[ESP_RINTR] = 0;
s->rregs[ESP_RSTAT] &= ~STAT_TC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_lower_irq(s); esp_lower_irq(s);
break;
return old_val;
default: default:
break; break;
} }